[S] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Update DPTF parameters

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87425?usp=email )

(

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/trulo/var/uldrenite: Update DPTF parameters
......................................................................

mb/google/trulo/var/uldrenite: Update DPTF parameters

Update the DPTF parameters as provided by thermal team.

1. Tcc_offset: 5 -> 3
2. Modify critical policy and passive policy setting

BUG=b:411866724
BRANCH=firmware-trulo-15217.771.B
TEST=build test firmware and verified by thermal team

Change-Id: Id5fda2e8c4985d41d0871454bb808a9cdfedc3e6
Signed-off-by: John Su 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87425
Reviewed-by: Kapil Porwal 
Tested-by: build bot (Jenkins) 
Reviewed-by: Dtrain Hsu 
---
M src/mainboard/google/brya/variants/uldrenite/overridetree.cb
1 file changed, 12 insertions(+), 12 deletions(-)

Approvals:
  Dtrain Hsu: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 55e1517..78fec3d 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -30,7 +30,7 @@
    # DPTF enable
    register "dptf_enable" = "true"

-	register "tcc_offset" = "5"     # TCC of 100
+	register "tcc_offset" = "3"

# Enable CNVi BT
    register "cnvi_bt_core" = "true"
@@ -194,17 +194,17 @@
    			## Passive Policy
    			register "policies.passive" = "{
    				[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
-					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 90, 5000),
-					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 90, 5000),
-					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 90, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 85, 5000),
+					[2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1, 85, 5000),
+					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 85, 5000),
    			}"

## Critical Policy
    			register "policies.critical" = "{
-					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
-					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     98, SHUTDOWN),
-					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     98, SHUTDOWN),
-					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     98, SHUTDOWN),
+					[0] = DPTF_CRITICAL(CPU,               130, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     105, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     105, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     105, SHUTDOWN),
    			}"

register "controls.power_limits" = "{
@@ -213,14 +213,14 @@
    					.max_power = 10000,
    					.time_window_min = 28 * MSECS_PER_SEC,
    					.time_window_max = 28 * MSECS_PER_SEC,
-						.granularity = 500
+						.granularity = 125
    				},
    				.pl2 = {
    					.min_power = 25000,
    					.max_power = 25000,
-						.time_window_min = 32 * MSECS_PER_SEC,
-						.time_window_max = 32 * MSECS_PER_SEC,
-						.granularity = 500
+						.time_window_min = 28 * MSECS_PER_SEC,
+						.time_window_max = 28 * MSECS_PER_SEC,
+						.granularity = 1000
    				}
    			}"