Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports

[Benjamin Doron (Code Review)]

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39538

to look at the new patch set (#5).

Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
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soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports

Port of CB:39412 for Skylake. Exposes PcieRpAspm and PcieRpL1Substates
to devicetree to allow boards to set these options

Chip config parameter PcieRpL1Substates uses (UPD value + 1)
because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
In order to ensure that mainboard setting does not disable L1 substates
incorrectly, chip config parameter values are offset by 1 with 0 meaning
use FSP UPD default.

get_l1_substate_control() ensures that the right UPD value is set in
fsp_params.

Chip config parameter values
0: Use FSP UPD default
1: Disable L1 substates
2: Use L1.1
3: Use L1.2 (FSP UPD default)

Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron 
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 35 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/5