flora.fu@mediatek.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58969 )
Change subject: soc/mediatek/mt8195: Add APU device apc driver ......................................................................
soc/mediatek/mt8195: Add APU device apc driver
Add APU device apc driver and setup permissions.
BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly
Signed-off-by: Flora Fu flora.fu@mediatek.com Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/apusys_devapc.h A src/soc/mediatek/mt8195/include/soc/apusys_devapc_def.h 6 files changed, 523 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58969/1
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index f99fa33..8cec51d 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -23,6 +23,7 @@ verstage-y += ../common/wdt.c
ramstage-y += apusys.c +ramstage-y += apusys_devapc.c romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += ../common/clkbuf.c diff --git a/src/soc/mediatek/mt8195/apusys_devapc.c b/src/soc/mediatek/mt8195/apusys_devapc.c new file mode 100644 index 0000000..3a7b9d0 --- /dev/null +++ b/src/soc/mediatek/mt8195/apusys_devapc.c @@ -0,0 +1,408 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/apusys_devapc.h> +#include <soc/apusys_devapc_def.h> + +/* For AO-0, AO-1 */ +#define SLAVE_FORBID_EXCEPT_D0_NO_PORTECT(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN) + +/* For AO-5 */ +#define SLAVE_NO_PROTECT_EXCEPT_D0_SEC_RW(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + SEC_RW_ONLY, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION) + +/* For VPUs */ +#define SLAVE_FORBID_EXCEPT_D0_D5_NO_PORTECT(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN) + +/* For Reviser, AO, DPAC, IOMMU Bank1~4 */ +#define SLAVE_FORBID_EXCEPT_D0_SEC_RW(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN) + +/* For apu_noc_config_0/1/2 */ +#define SLAVE_FORBID_EXCEPT_D0_D3_NO_PORTECT(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN) + +/* For Others */ +#define SLAVE_NO_PROTECT(domain) \ + APUSYS_APC_AO_ATTR(domain, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, \ + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION) + + +/* NOC DAPC */ +static const struct APC_DOM_16 APUSYS_NOC_DAPC_AO[] = { +/* 0 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv00-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv00-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv00-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv01-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv01-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv01-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv03-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv03-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv03-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv03-3"), +/* 10 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv03-4"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv04_05_06_07-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv04_05_06_07-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv04_05_06_07-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("slv04_05_06_07-3"), +}; + +static const struct APC_DOM_16 APUSYS_AO_Devices[] = { +/* 0 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-1"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apusys_ao-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-3"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-4"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-5"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apusys_ao-6"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apusys_ao-8"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apusys_ao-9"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("md32_apb_s-0"), + +/* 10 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("md32_apb_s-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("md32_apb_s-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("md32_debug_apb"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_con2_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_con1_config"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_sctrl_reviscer"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_sema_stimer"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_emi_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_edma0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_edma1"), + +/* 20 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_cpe_sensor"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_cpe_coef"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_cpe_ctrl"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_sensor_wrp_dla_0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_sensor_wrp_dla_1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_dapc_ao"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_dapc"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("infra_bcrm"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("infra_ao_bcrm"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("noc_dapc"), + +/* 30 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_noc_bcrm"), +SLAVE_FORBID_EXCEPT_D0_D3_NO_PORTECT("apu_noc_config_0"), +SLAVE_FORBID_EXCEPT_D0_D3_NO_PORTECT("apu_noc_config_1"), +SLAVE_FORBID_EXCEPT_D0_D3_NO_PORTECT("apu_noc_config_2"), +SLAVE_FORBID_EXCEPT_D0_D5_NO_PORTECT("vpu_core0_config-0"), +SLAVE_FORBID_EXCEPT_D0_D5_NO_PORTECT("vpu_core0_config-1"), +SLAVE_FORBID_EXCEPT_D0_D5_NO_PORTECT("vpu_core1_config-0"), +SLAVE_FORBID_EXCEPT_D0_D5_NO_PORTECT("vpu_core1_config-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla0_apb-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla0_apb-1"), + +/* 40 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla0_apb-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla0_apb-3"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla1_apb-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla1_apb-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla1_apb-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("mdla1_apb-3"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_iommu0_r0"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu0_r1"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu0_r2"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu0_r3"), + +/* 50 */ +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu0_r4"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_iommu1_r0"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu1_r1"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu1_r2"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu1_r3"), +SLAVE_FORBID_EXCEPT_D0_SEC_RW("apu_iommu1_r4"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_rsi2_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_s0_ssc_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_n0_ssc_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_acp_ssc_config"), + +/* 60 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_s1_ssc_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_n1_ssc_config"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-0"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-1"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-2"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-3"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-4"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apu_ao_dbgapb-5"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("vpu_core0_debug_apb"), +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("vpu_core1_debug_apb"), + +/* 70 */ +SLAVE_FORBID_EXCEPT_D0_NO_PORTECT("apb_infra_dbg_ctl"), +}; + +static int set_slave_noc_dapc(u32 slave, + enum APUSYS_APC_DOMAIN_ID domain_id, + enum APUSYS_APC_PERM_TYPE perm) +{ + u32 apc_register_index; + u32 apc_set_index; + u32 *base = NULL; + u32 clr_bit; + u32 set_bit; + int ret; + + if (perm >= PERM_NUM || perm < 0) { + printk(BIOS_DEBUG, "[NOC_DAPC] permission type:0x%x is not supported!\n", + perm); + ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + goto exit; + } + + apc_register_index = slave / APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + + clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2)); + set_bit = ((u32)perm) << (apc_set_index * 2); + + if (slave < APUSYS_NOC_DAPC_AO_SLAVE_NUM && + domain_id < APUSYS_NOC_DAPC_AO_DOM_NUM) { + base = (u32 *)((size_t)APUSYS_NOC_DAPC_AO_BASE + + domain_id * 0x40 + apc_register_index * 4); + apuapc_writel(apuapc_readl(base) & clr_bit, base); + apuapc_writel(apuapc_readl(base) | set_bit, base); + ret = APUSYS_APC_OK; + } else { + printk(BIOS_DEBUG, "[NOC_DAPC] %s: %s, %s:0x%x, %s:0x%x\n", + __func__, "out of boundary", + "slave", slave, + "domain_id", domain_id); + ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + +exit: + return ret; +} + +static void dump_apusys_noc_dapc(void) +{ + u32 reg_num; + u32 d, i; + + reg_num = APUSYS_NOC_DAPC_AO_SLAVE_NUM / + APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) { + for (i = 0U; i <= reg_num; i++) + printk(BIOS_DEBUG, "[NOCDAPC] D%d_APC_%d: 0x%x\n", d, i, + apuapc_readl(APUSYS_NOC_DAPC_AO_BASE + + d * 0x40 + i * 4)); + } + printk(BIOS_DEBUG, "[NOCDAPC] APC_CON: 0x%x\n", + apuapc_readl(APUSYS_NOC_DAPC_CON)); +} + +static int set_slave_apc(u32 slave, + enum APUSYS_APC_DOMAIN_ID domain_id, + enum APUSYS_APC_PERM_TYPE perm) +{ + u32 apc_register_index; + u32 apc_set_index; + u32 *base = NULL; + u32 clr_bit; + u32 set_bit; + int ret; + + if (perm >= PERM_NUM) { + printk(BIOS_DEBUG, "[APUAPC] perm type:0x%x is not supported!\n", + perm); + ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + goto exit; + } + + apc_register_index = slave / APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + + clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2)); + set_bit = perm << (apc_set_index * 2); + + if (slave < APUSYS_APC_SYS0_AO_SLAVE_NUM && + domain_id < APUSYS_APC_SYS0_AO_DOM_NUM) { + base = (u32 *)((size_t)APUSYS_APC_AO_BASE + + domain_id * 0x40 + apc_register_index * 4); + apuapc_writel(apuapc_readl(base) & clr_bit, base); + apuapc_writel(apuapc_readl(base) | set_bit, base); + ret = APUSYS_APC_OK; + } else { + printk(BIOS_DEBUG, "[APUAPC] %s: %s, %s:0x%x, %s:0x%x\n", + __func__, "out of boundary", + "slave", slave, + "domain_id", domain_id); + ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + +exit: + return ret; +} + +static void dump_apusys_ao_apc(void) +{ + u32 reg_num; + u32 d, i; + + reg_num = APUSYS_APC_SYS0_AO_SLAVE_NUM / + APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) { + for (i = 0U; i <= reg_num; i++) + printk(BIOS_DEBUG, "[APUAPC] D%d_APC_%d: 0x%x\n", d, i, + apuapc_readl(APUSYS_APC_AO_BASE + + d * 0x40 + i * 4)); + } + printk(BIOS_DEBUG, "[APUAPC] APC_CON: 0x%x\n", + apuapc_readl(APUSYS_APC_CON)); +} + +static int set_apusys_noc_dapc(void) +{ + int ret = APUSYS_APC_OK; + u32 i; + + for (i = 0; i < ARRAY_SIZE(APUSYS_NOC_DAPC_AO); i++) { + ret += set_slave_noc_dapc(i, DOMAIN_0, + APUSYS_NOC_DAPC_AO[i].d0_permission); + ret += set_slave_noc_dapc(i, DOMAIN_1, + APUSYS_NOC_DAPC_AO[i].d1_permission); + ret += set_slave_noc_dapc(i, DOMAIN_2, + APUSYS_NOC_DAPC_AO[i].d2_permission); + ret += set_slave_noc_dapc(i, DOMAIN_3, + APUSYS_NOC_DAPC_AO[i].d3_permission); + ret += set_slave_noc_dapc(i, DOMAIN_4, + APUSYS_NOC_DAPC_AO[i].d4_permission); + ret += set_slave_noc_dapc(i, DOMAIN_5, + APUSYS_NOC_DAPC_AO[i].d5_permission); + ret += set_slave_noc_dapc(i, DOMAIN_6, + APUSYS_NOC_DAPC_AO[i].d6_permission); + ret += set_slave_noc_dapc(i, DOMAIN_7, + APUSYS_NOC_DAPC_AO[i].d7_permission); + ret += set_slave_noc_dapc(i, DOMAIN_8, + APUSYS_NOC_DAPC_AO[i].d8_permission); + ret += set_slave_noc_dapc(i, DOMAIN_9, + APUSYS_NOC_DAPC_AO[i].d9_permission); + ret += set_slave_noc_dapc(i, DOMAIN_10, + APUSYS_NOC_DAPC_AO[i].d10_permission); + ret += set_slave_noc_dapc(i, DOMAIN_11, + APUSYS_NOC_DAPC_AO[i].d11_permission); + ret += set_slave_noc_dapc(i, DOMAIN_12, + APUSYS_NOC_DAPC_AO[i].d12_permission); + ret += set_slave_noc_dapc(i, DOMAIN_13, + APUSYS_NOC_DAPC_AO[i].d13_permission); + ret += set_slave_noc_dapc(i, DOMAIN_14, + APUSYS_NOC_DAPC_AO[i].d14_permission); + ret += set_slave_noc_dapc(i, DOMAIN_15, + APUSYS_NOC_DAPC_AO[i].d15_permission); + } + + return ret; +} + +static int32_t set_apusys_ao_apc(void) +{ + int ret = APUSYS_APC_OK; + u32 i; + + for (i = 0; i < ARRAY_SIZE(APUSYS_AO_Devices); i++) { + /* d0: APMCU */ + ret += set_slave_apc(i, DOMAIN_0, + APUSYS_AO_Devices[i].d0_permission); + ret += set_slave_apc(i, DOMAIN_1, + APUSYS_AO_Devices[i].d1_permission); + ret += set_slave_apc(i, DOMAIN_2, + APUSYS_AO_Devices[i].d2_permission); + ret += set_slave_apc(i, DOMAIN_3, + APUSYS_AO_Devices[i].d3_permission); + ret += set_slave_apc(i, DOMAIN_4, + APUSYS_AO_Devices[i].d4_permission); + ret += set_slave_apc(i, DOMAIN_5, + APUSYS_AO_Devices[i].d5_permission); + ret += set_slave_apc(i, DOMAIN_6, + APUSYS_AO_Devices[i].d6_permission); + ret += set_slave_apc(i, DOMAIN_7, + APUSYS_AO_Devices[i].d7_permission); + ret += set_slave_apc(i, DOMAIN_8, + APUSYS_AO_Devices[i].d8_permission); + ret += set_slave_apc(i, DOMAIN_9, + APUSYS_AO_Devices[i].d9_permission); + ret += set_slave_apc(i, DOMAIN_10, + APUSYS_AO_Devices[i].d10_permission); + ret += set_slave_apc(i, DOMAIN_11, + APUSYS_AO_Devices[i].d11_permission); + ret += set_slave_apc(i, DOMAIN_12, + APUSYS_AO_Devices[i].d12_permission); + ret += set_slave_apc(i, DOMAIN_13, + APUSYS_AO_Devices[i].d13_permission); + ret += set_slave_apc(i, DOMAIN_14, + APUSYS_AO_Devices[i].d14_permission); + ret += set_slave_apc(i, DOMAIN_15, + APUSYS_AO_Devices[i].d15_permission); + } + + return ret; +} + +static void set_apc_lock(void) +{ + /* Lock apu_sctrl_reviser */ + u32 set_bit = 1U << APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER; + + set_bit = set_bit | (1U << APUSYS_APC_SYS0_LOCK_BIT_DEVAPC_AO_WRAPPER); + apuapc_writel(set_bit, APUSYS_SYS0_APC_LOCK_0); +} + +void start_apusys_devapc(void) +{ + int ret = APUSYS_APC_OK; + + /* Check violation status */ + printk(BIOS_DEBUG, "[APUAPC] vio %d\n", + apuapc_readl(APUSYS_APC_CON) & 0x80000000); + + /* Initial Permission */ + ret = set_apusys_ao_apc(); + printk(BIOS_DEBUG, "[APUAPC] %s - %s!\n", "set_apusys_ao_apc", + ret ? "FAILED" : "SUCCESS"); + + /* Lock */ + set_apc_lock(); + + /* Initial NoC Permission */ + ret = set_apusys_noc_dapc(); + printk(BIOS_DEBUG, "[APUAPC] %s - %s!\n", "set_apusys_noc_dapc", + ret ? "FAILED" : "SUCCESS"); + + dump_apusys_ao_apc(); + dump_apusys_noc_dapc(); + + printk(BIOS_DEBUG, "[APUAPC] %s done\n", __func__); +} + diff --git a/src/soc/mediatek/mt8195/devapc.c b/src/soc/mediatek/mt8195/devapc.c index 9354353..3639ad5 100644 --- a/src/soc/mediatek/mt8195/devapc.c +++ b/src/soc/mediatek/mt8195/devapc.c @@ -2,6 +2,7 @@
#include <console/console.h> #include <soc/devapc.h> +#include <soc/apusys_devapc.h>
static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { /* 0 */ @@ -1884,4 +1885,7 @@ if (devapc_init[i].dump) devapc_init[i].dump(devapc_ao_base); } + + /* Setup APUSYS Permission */ + start_apusys_devapc(); } diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index cbe704c..d9486b3 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -81,6 +81,8 @@ IOCFG_TL_BASE = IO_PHYS + 0x01F40000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, APU_MBOX_BASE = IO_PHYS + 0x09000000, + APUSYS_APC_AO_BASE = IO_PHYS + 0x090F8000, + APUSYS_NOC_DAPC_AO_BASE = IO_PHYS + 0x090FC000, DISP_OVL0_BASE = IO_PHYS + 0x0C000000, DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, diff --git a/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h b/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h new file mode 100644 index 0000000..fa8cb80 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef APUSYS_DEVAPC_H +#define APUSYS_DEVAPC_H + +void start_apusys_devapc(void); + +#endif /* APUSYS_DEVAPC_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/apusys_devapc_def.h b/src/soc/mediatek/mt8195/include/soc/apusys_devapc_def.h new file mode 100644 index 0000000..e0d7cbf --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/apusys_devapc_def.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef APUSYS_DEVAPC_DEF_H +#define APUSYS_DEVAPC_DEF_H + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <types.h> + +enum APUSYS_APC_ERR_STATUS { + APUSYS_APC_OK = 0x0, + + APUSYS_APC_ERR_GENERIC = 0x1000, + APUSYS_APC_ERR_INVALID_CMD = 0x1001, + APUSYS_APC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002, + APUSYS_APC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003, + APUSYS_APC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004, + APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005, + APUSYS_APC_ERR_OUT_OF_BOUNDARY = 0x1006, + APUSYS_APC_ERR_REQ_TYPE_NOT_SUPPORTED = 0x1007, +}; + +enum APUSYS_APC_PERM_TYPE { + NO_PROTECTION = 0U, + SEC_RW_ONLY = 1U, + SEC_RW_NS_R = 2U, + FORBIDDEN = 3U, + PERM_NUM = 4U, +}; + +enum APUSYS_APC_DOMAIN_ID { + DOMAIN_0 = 0U, + DOMAIN_1 = 1U, + DOMAIN_2 = 2U, + DOMAIN_3 = 3U, + DOMAIN_4 = 4U, + DOMAIN_5 = 5U, + DOMAIN_6 = 6U, + DOMAIN_7 = 7U, + DOMAIN_8 = 8U, + DOMAIN_9 = 9U, + DOMAIN_10 = 10U, + DOMAIN_11 = 11U, + DOMAIN_12 = 12U, + DOMAIN_13 = 13U, + DOMAIN_14 = 14U, + DOMAIN_15 = 15U, +}; + +struct APC_DOM_16 { + unsigned char d0_permission; + unsigned char d1_permission; + unsigned char d2_permission; + unsigned char d3_permission; + unsigned char d4_permission; + unsigned char d5_permission; + unsigned char d6_permission; + unsigned char d7_permission; + unsigned char d8_permission; + unsigned char d9_permission; + unsigned char d10_permission; + unsigned char d11_permission; + unsigned char d12_permission; + unsigned char d13_permission; + unsigned char d14_permission; + unsigned char d15_permission; +}; + +#define APUSYS_APC_AO_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) \ + {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \ + (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \ + (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \ + (unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \ + (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \ + (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \ + (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15} + +#define apuapc_writel(val, reg) write32((void *)reg, val) +#define apuapc_readl(reg) read32((void *)reg) + +#define APUSYS_APC_CON ((u32 *)(APUSYS_APC_AO_BASE + 0x00F00)) +#define APUSYS_SYS0_APC_LOCK_0 ((u32 *)(APUSYS_APC_AO_BASE + 0x00700)) +#define APUSYS_NOC_DAPC_CON ((u32 *)(APUSYS_NOC_DAPC_AO_BASE + 0x00F00)) + +#define APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_APC_SYS0_AO_DOM_NUM 16U +#define APUSYS_APC_SYS0_AO_SLAVE_NUM 71U + +#define APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER 15U +#define APUSYS_APC_SYS0_LOCK_BIT_DEVAPC_AO_WRAPPER 8U + +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_NOC_DAPC_AO_DOM_NUM 16U +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM 27U +#endif /* APUSYS_DEVAPC_DEF_H */
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