[XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Nill Ge, Reka Norman, Shuo Liu, TangYiwei, Tim Chu.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email )

Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
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Patch Set 3:

(1 comment)

Patchset:

PS1:
> > > MRC_WRITE_NV_LATE doesn't work. To summarize for SPR-SP, fsp_find_nv_storage_data() must be called after FSP-S has returned, because FSP_NON_VOLATILE_STORAGE_HOB is created in FSP-S.
> >
> > This is just violation of the spec where FSP-M should implement the FSP_NON_VOLATILE_STORAGE_HOB and not the FSP-S.
>
> As per FSP 2.4 specification , section 11.3
> The bootloader needs to parse the HOB list to see if such a GUID HOB exists after
> memory is initialized. The HOB shall be populated either after returning from 
> FSP Output FspMemoryInit() in API mode or after all notification call backs for
> EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI are completed in dispatch mode
> > Due to this Intel FSP problem, we need to keep ugly W/A in coreboot.
> >
> > now I have better picture, let me think and come back with yet another attempt

I will bring this up with Intel FSP team during arch meetign. At this moment it sounded more W/A as implementation is not matching the spec