Change in coreboot[master]: soc/amd/cezanne: Port ACPI p-state and c-state entries from picasso

[Jason Glenesk (Code Review)]

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian, Felix Held.
Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52036 )

Change subject: soc/amd/cezanne: Port ACPI p-state and c-state entries from picasso
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Patch Set 5:

(5 comments)

This change is ready for review.

File src/soc/amd/cezanne/acpi.c:

https://review.coreboot.org/c/coreboot/+/52036/comment/d4008463_d524b807 
PS1, Line 8: #include <acpi/acpigen.h>
> Nit: Move it above "#include <amdblocks/acpi. […]

Done

https://review.coreboot.org/c/coreboot/+/52036/comment/6026e427_de25f753 
PS1, Line 295: 400
> Did you verify this?

carry over from the port. Fixed now.

https://review.coreboot.org/c/coreboot/+/52036/comment/95f0325c_f6ae1437 
PS1, Line 344: acpigen_write_CSD_package(cpu >> 1, threads_per_co
> this should be cpu / threads_per_core instead of cpu >> 1; see CB:51932

Pulled in the change felix recommended.
Karthik - Will move things into common after we get S0i working on Cezanne. It will be some effort adding stoney, picasso and this together.

File src/soc/amd/cezanne/include/soc/msr.h:

https://review.coreboot.org/c/coreboot/+/52036/comment/62a27b58_87712326 
PS1, Line 3: /* This file applies to AMD64 products.
           :  * The definitions come from the device's PPR.
           :  */
> Think we can remove this comment

Done

https://review.coreboot.org/c/coreboot/+/52036/comment/01328a18_0eecb4a8 
PS1, Line 7: _PICASS
> CEZANNE

Done