Change in coreboot[master]: soc/intel/broadwell: Inline single-use functions

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46989 )

Change subject: soc/intel/broadwell: Inline single-use functions
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soc/intel/broadwell: Inline single-use functions

These functions are only used in a single place, so inline them.

Change-Id: Iec47a7a1fd835080f6641afcbcfddf25e1d5f46a
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/haswell.h
M src/soc/intel/broadwell/northbridge.c
3 files changed, 7 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46989/1

diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 3a9ac13..300b7e7 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -74,8 +74,13 @@
    if (emit_igd) {
    	const unsigned long tmp = current;

-		current += acpi_create_dmar_rmrr(current, 0,
-				sa_get_gsm_base(), sa_get_tolud_base() - 1);
+		const struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+
+		/* Bit 0 is lock bit, not part of address */
+		const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1;
+		const u32 bgsm  = pci_read_config32(sa_dev,  BGSM) & ~1;
+
+		current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1);
    	current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
    	acpi_dmar_rmrr_fixup(tmp, current);
    }
diff --git a/src/soc/intel/broadwell/haswell.h b/src/soc/intel/broadwell/haswell.h
index 09de2ef..2ce068a 100644
--- a/src/soc/intel/broadwell/haswell.h
+++ b/src/soc/intel/broadwell/haswell.h
@@ -155,9 +155,6 @@
 /* System Agent identification */
 u8 systemagent_revision(void);

-uintptr_t sa_get_tolud_base(void);
-uintptr_t sa_get_gsm_base(void);
-
 void systemagent_early_init(void);

u32 igd_get_reg_em4(void);
diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c
index 4e75721..2163a14 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/soc/intel/broadwell/northbridge.c
@@ -22,20 +22,6 @@
    return pci_read_config8(sa_dev, PCI_REVISION_ID);
 }

-uintptr_t sa_get_tolud_base(void)
-{
-	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
-	/* Bit 0 is lock bit, not part of address */
-	return pci_read_config32(sa_dev, TOLUD) & ~1;
-}
-
-uintptr_t sa_get_gsm_base(void)
-{
-	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
-	/* Bit 0 is lock bit, not part of address */
-	return pci_read_config32(sa_dev, BGSM) & ~1;
-}
-
 static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
 {
    u32 pciexbar_reg;