HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37454 )
Change subject: {nb,soc}: Add missing <commonlib/helpers.h> ......................................................................
{nb,soc}: Add missing <commonlib/helpers.h>
Use MIN() and MAX() defined in commonlib/helpers.h
Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/soc/amd/common/block/spi/fch_spi_flash.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/smbios.c M src/soc/intel/quark/i2c.c M src/soc/intel/skylake/elog.c 7 files changed, 39 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37454/1
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 7f59d91..720bd64 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -17,6 +17,7 @@ #include <cf9_reset.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <delay.h> @@ -364,15 +365,15 @@ u32 maxtrtp = 0;
FOR_EACH_POPULATED_DIMM(s->dimms, i) { - maxtras = max(maxtras, s->dimms[i].spd_data[30] * 1000); - maxtrp = max(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); - maxtrcd = max(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); - maxtwr = max(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); - maxtrfc = max(maxtrfc, s->dimms[i].spd_data[42] * 1000 + + maxtras = MAX(maxtras, s->dimms[i].spd_data[30] * 1000); + maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); + maxtrcd = MAX(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); + maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); + maxtrfc = MAX(maxtrfc, s->dimms[i].spd_data[42] * 1000 + (s->dimms[i].spd_data[40] & 0xf)); - maxtwtr = max(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); - maxtrrd = max(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); - maxtrtp = max(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); + maxtwtr = MAX(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); + maxtrrd = MAX(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); + maxtrtp = MAX(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); } /* * TODO: on ddr3 there might be some minimal required values for some @@ -456,7 +457,7 @@ // Start with fastest common CAS cas = 0; highcas = msbp; - lowcas = max(lsbp, 5); + lowcas = MAX(lsbp, 5);
while (cas == 0 && highcas >= lowcas) { FOR_EACH_POPULATED_DIMM(s->dimms, i) { diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4974173..44e5d3a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */
+#include <commonlib/helpers.h> #include <console/console.h> #include <string.h> #include <arch/cpu.h> @@ -1461,7 +1462,7 @@ /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16); MCHBAR32(0x4210 + 0x400 * channel) = 0x244; @@ -1499,7 +1500,7 @@ /* DRAM command ACT */ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4234 + 0x400 * channel) = - (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; MCHBAR32(0x4214 + 0x400 * channel) = 0x244; @@ -1507,7 +1508,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x40011f4 | (max(ctrl->tRTP, 8) << 16); + 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
@@ -2101,7 +2102,7 @@ /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) + ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | ctr | 0x60000; @@ -2118,7 +2119,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x4001020 | (max(ctrl->tRTP, 8) << 16); + 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd; MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42; @@ -2662,7 +2663,7 @@ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = 0x4 | (ctrl->tRCD << 16) | - (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; @@ -2679,7 +2680,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x4005020 | (max(ctrl->tRTP, 8) << 16); + 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; MCHBAR32(0x4218 + 0x400 * channel) = 0x242; @@ -2717,9 +2718,9 @@ rn.end, rn.start + ctrl->edge_offset[i], rn.end - ctrl->edge_offset[i]); lower[lane] = - max(rn.start + ctrl->edge_offset[i], lower[lane]); + MAX(rn.start + ctrl->edge_offset[i], lower[lane]); upper[lane] = - min(rn.end - ctrl->edge_offset[i], upper[lane]); + MIN(rn.end - ctrl->edge_offset[i], upper[lane]); edges[lane] = (lower[lane] + upper[lane]) / 2; if (rn.all || (lower[lane] > upper[lane])) { printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", @@ -2787,7 +2788,7 @@ /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; @@ -2803,7 +2804,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x40011e0 | (max(ctrl->tRTP, 8) << 16); + 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
@@ -2883,10 +2884,10 @@ rn.start + ctrl->timC_offset[i], rn.end - ctrl->timC_offset[i]); lower[channel][slotrank][lane] = - max(rn.start + ctrl->timC_offset[i], + MAX(rn.start + ctrl->timC_offset[i], lower[channel][slotrank][lane]); upper[channel][slotrank][lane] = - min(rn.end - ctrl->timC_offset[i], + MIN(rn.end - ctrl->timC_offset[i], upper[channel][slotrank][lane]);
} @@ -2927,7 +2928,7 @@ int delta; mat = 0; FOR_ALL_LANES mat = - max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); + MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); printram("normalize %d, %d, %d: mat %d\n", channel, slotrank, lane, mat);
@@ -3080,8 +3081,8 @@ int max_320c = -10000;
FOR_ALL_POPULATED_RANKS { - max_320c = max(ctrl->timings[channel][slotrank].val_320c, max_320c); - min_320c = min(ctrl->timings[channel][slotrank].val_320c, min_320c); + max_320c = MAX(ctrl->timings[channel][slotrank].val_320c, max_320c); + min_320c = MIN(ctrl->timings[channel][slotrank].val_320c, min_320c); }
if (max_320c - min_320c > 51) diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c index 40dd0e2..1f6e4f2 100644 --- a/src/soc/amd/common/block/spi/fch_spi_flash.c +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <commonlib/helpers.h> #include <console/console.h> #include <spi_flash.h> #include <soc/southbridge.h> @@ -31,7 +32,7 @@
static int crop_chunk(unsigned int cmd_len, unsigned int buf_len) { - return min((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len); + return MIN((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len); }
int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) @@ -192,7 +193,7 @@
for (actual = start; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = crop_chunk(sizeof(cmd), chunk_len);
cmd[0] = spi_data_ptr->write_cmd; diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 0a43442..f887b3c 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -14,6 +14,7 @@ */
#include <device/mmio.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <fast_spi_def.h> #include <intelblocks/fast_spi.h> @@ -157,11 +158,11 @@ static size_t get_xfer_len(const struct spi_flash *flash, uint32_t addr, size_t len) { - size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); + size_t xfer_len = MIN(len, SPIBAR_FDATA_FIFO_SIZE); size_t bytes_left = ALIGN_UP(addr, flash->page_size) - addr;
if (bytes_left) - xfer_len = min(xfer_len, bytes_left); + xfer_len = MIN(xfer_len, bytes_left);
return xfer_len; } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d315e15..e1b71ba 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -16,6 +16,7 @@ #include <smbios.h> #include "smbios.h" #include <string.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <device/dram/ddr3.h>
@@ -63,7 +64,7 @@
strncpy((char *)dimm->module_part_number, module_part_num, - min(sizeof(dimm->module_part_number), + MIN(sizeof(dimm->module_part_number), module_part_number_size)); if (module_serial_num) memcpy(dimm->serial, module_serial_num, diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index b09852b..1d17a7c 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -14,6 +14,7 @@ */
#include <assert.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> #include <device/device.h> @@ -133,7 +134,7 @@ }
/* Fill the FIFO with read commands */ - fifo_bytes = min(length, 16); + fifo_bytes = MIN(length, 16); bytes_transferred = 0; while (length > 0) { status = regs->ic_raw_intr_stat; diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 7951394..411b3e9 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -16,6 +16,7 @@
#include <bootstate.h> #include <cbmem.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -156,7 +157,7 @@ { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, };
- maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); + maxports = MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info));
for (i = 0; i < maxports; i++) { dev = pme_status_info[i].dev;
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37454 )
Change subject: {nb,soc}: Add missing <commonlib/helpers.h> ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/37454/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37454/4//COMMIT_MSG@7 PS4, Line 7: {nb,soc}: Add missing <commonlib/helpers.h> {nb,soc}: Replace min/max() with MIN/MAX()
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37454 )
Change subject: {nb,soc}: Add missing <commonlib/helpers.h> ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37454/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37454/4//COMMIT_MSG@7 PS4, Line 7: {nb,soc}: Add missing <commonlib/helpers.h>
{nb,soc}: Replace min/max() with MIN/MAX()
Done
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37454
to look at the new patch set (#5).
Change subject: Replace min/max() with MIN/MAX() ......................................................................
Replace min/max() with MIN/MAX()
Use MIN() and MAX() defined in commonlib/helpers.h
Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/soc/amd/common/block/spi/fch_spi_flash.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/smbios.c M src/soc/intel/quark/i2c.c M src/soc/intel/skylake/elog.c 7 files changed, 39 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37454/5
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins), Damien Zammit,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37454
to look at the new patch set (#6).
Change subject: {nb,soc}: Replace min/max() with MIN/MAX() ......................................................................
{nb,soc}: Replace min/max() with MIN/MAX()
Use MIN() and MAX() defined in commonlib/helpers.h
Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/soc/amd/common/block/spi/fch_spi_flash.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/smbios.c M src/soc/intel/quark/i2c.c M src/soc/intel/skylake/elog.c 7 files changed, 39 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37454/6
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37454 )
Change subject: {nb,soc}: Replace min/max() with MIN/MAX() ......................................................................
Patch Set 6: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37454 )
Change subject: {nb,soc}: Replace min/max() with MIN/MAX() ......................................................................
Patch Set 7: Code-Review+1
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37454 )
Change subject: {nb,soc}: Replace min/max() with MIN/MAX() ......................................................................
Patch Set 7: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37454 )
Change subject: {nb,soc}: Replace min/max() with MIN/MAX() ......................................................................
{nb,soc}: Replace min/max() with MIN/MAX()
Use MIN() and MAX() defined in commonlib/helpers.h
Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/37454 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/soc/amd/common/block/spi/fch_spi_flash.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/smbios.c M src/soc/intel/quark/i2c.c M src/soc/intel/skylake/elog.c 7 files changed, 39 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Kyösti Mälkki: Looks good to me, but someone else must approve
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 7f59d91..720bd64 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -17,6 +17,7 @@ #include <cf9_reset.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <delay.h> @@ -364,15 +365,15 @@ u32 maxtrtp = 0;
FOR_EACH_POPULATED_DIMM(s->dimms, i) { - maxtras = max(maxtras, s->dimms[i].spd_data[30] * 1000); - maxtrp = max(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); - maxtrcd = max(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); - maxtwr = max(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); - maxtrfc = max(maxtrfc, s->dimms[i].spd_data[42] * 1000 + + maxtras = MAX(maxtras, s->dimms[i].spd_data[30] * 1000); + maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); + maxtrcd = MAX(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); + maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); + maxtrfc = MAX(maxtrfc, s->dimms[i].spd_data[42] * 1000 + (s->dimms[i].spd_data[40] & 0xf)); - maxtwtr = max(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); - maxtrrd = max(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); - maxtrtp = max(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); + maxtwtr = MAX(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); + maxtrrd = MAX(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); + maxtrtp = MAX(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); } /* * TODO: on ddr3 there might be some minimal required values for some @@ -456,7 +457,7 @@ // Start with fastest common CAS cas = 0; highcas = msbp; - lowcas = max(lsbp, 5); + lowcas = MAX(lsbp, 5);
while (cas == 0 && highcas >= lowcas) { FOR_EACH_POPULATED_DIMM(s->dimms, i) { diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4974173..44e5d3a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */
+#include <commonlib/helpers.h> #include <console/console.h> #include <string.h> #include <arch/cpu.h> @@ -1461,7 +1462,7 @@ /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16); MCHBAR32(0x4210 + 0x400 * channel) = 0x244; @@ -1499,7 +1500,7 @@ /* DRAM command ACT */ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4234 + 0x400 * channel) = - (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; MCHBAR32(0x4214 + 0x400 * channel) = 0x244; @@ -1507,7 +1508,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x40011f4 | (max(ctrl->tRTP, 8) << 16); + 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
@@ -2101,7 +2102,7 @@ /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) + ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | ctr | 0x60000; @@ -2118,7 +2119,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x4001020 | (max(ctrl->tRTP, 8) << 16); + 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd; MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42; @@ -2662,7 +2663,7 @@ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = 0x4 | (ctrl->tRCD << 16) | - (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; @@ -2679,7 +2680,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x4005020 | (max(ctrl->tRTP, 8) << 16); + 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; MCHBAR32(0x4218 + 0x400 * channel) = 0x242; @@ -2717,9 +2718,9 @@ rn.end, rn.start + ctrl->edge_offset[i], rn.end - ctrl->edge_offset[i]); lower[lane] = - max(rn.start + ctrl->edge_offset[i], lower[lane]); + MAX(rn.start + ctrl->edge_offset[i], lower[lane]); upper[lane] = - min(rn.end - ctrl->edge_offset[i], upper[lane]); + MIN(rn.end - ctrl->edge_offset[i], upper[lane]); edges[lane] = (lower[lane] + upper[lane]) / 2; if (rn.all || (lower[lane] > upper[lane])) { printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n", @@ -2787,7 +2788,7 @@ /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; MCHBAR32(0x4230 + 0x400 * channel) = - (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; @@ -2803,7 +2804,7 @@ /* DRAM command RD */ MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; MCHBAR32(0x4238 + 0x400 * channel) = - 0x40011e0 | (max(ctrl->tRTP, 8) << 16); + 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
@@ -2883,10 +2884,10 @@ rn.start + ctrl->timC_offset[i], rn.end - ctrl->timC_offset[i]); lower[channel][slotrank][lane] = - max(rn.start + ctrl->timC_offset[i], + MAX(rn.start + ctrl->timC_offset[i], lower[channel][slotrank][lane]); upper[channel][slotrank][lane] = - min(rn.end - ctrl->timC_offset[i], + MIN(rn.end - ctrl->timC_offset[i], upper[channel][slotrank][lane]);
} @@ -2927,7 +2928,7 @@ int delta; mat = 0; FOR_ALL_LANES mat = - max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); + MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); printram("normalize %d, %d, %d: mat %d\n", channel, slotrank, lane, mat);
@@ -3080,8 +3081,8 @@ int max_320c = -10000;
FOR_ALL_POPULATED_RANKS { - max_320c = max(ctrl->timings[channel][slotrank].val_320c, max_320c); - min_320c = min(ctrl->timings[channel][slotrank].val_320c, min_320c); + max_320c = MAX(ctrl->timings[channel][slotrank].val_320c, max_320c); + min_320c = MIN(ctrl->timings[channel][slotrank].val_320c, min_320c); }
if (max_320c - min_320c > 51) diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c index 72bc5d6..d8eeefc 100644 --- a/src/soc/amd/common/block/spi/fch_spi_flash.c +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <commonlib/helpers.h> #include <console/console.h> #include <spi_flash.h> #include <soc/southbridge.h> @@ -31,7 +32,7 @@
static int crop_chunk(unsigned int cmd_len, unsigned int buf_len) { - return min((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len); + return MIN((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len); }
int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) @@ -192,7 +193,7 @@
for (actual = start; actual < len; actual += chunk_len) { byte_addr = offset % page_size; - chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = MIN(len - actual, page_size - byte_addr); chunk_len = crop_chunk(sizeof(cmd), chunk_len);
cmd[0] = spi_data_ptr->write_cmd; diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 0a43442..f887b3c 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -14,6 +14,7 @@ */
#include <device/mmio.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <fast_spi_def.h> #include <intelblocks/fast_spi.h> @@ -157,11 +158,11 @@ static size_t get_xfer_len(const struct spi_flash *flash, uint32_t addr, size_t len) { - size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); + size_t xfer_len = MIN(len, SPIBAR_FDATA_FIFO_SIZE); size_t bytes_left = ALIGN_UP(addr, flash->page_size) - addr;
if (bytes_left) - xfer_len = min(xfer_len, bytes_left); + xfer_len = MIN(xfer_len, bytes_left);
return xfer_len; } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d315e15..e1b71ba 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -16,6 +16,7 @@ #include <smbios.h> #include "smbios.h" #include <string.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <device/dram/ddr3.h>
@@ -63,7 +64,7 @@
strncpy((char *)dimm->module_part_number, module_part_num, - min(sizeof(dimm->module_part_number), + MIN(sizeof(dimm->module_part_number), module_part_number_size)); if (module_serial_num) memcpy(dimm->serial, module_serial_num, diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 7ff2ddf..6430030 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -14,6 +14,7 @@ */
#include <assert.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> #include <device/device.h> @@ -133,7 +134,7 @@ }
/* Fill the FIFO with read commands */ - fifo_bytes = min(length, 16); + fifo_bytes = MIN(length, 16); bytes_transferred = 0; while (length > 0) { status = regs->ic_raw_intr_stat; diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 7951394..411b3e9 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -16,6 +16,7 @@
#include <bootstate.h> #include <cbmem.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -156,7 +157,7 @@ { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, };
- maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); + maxports = MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info));
for (i = 0; i < maxports; i++) { dev = pme_status_info[i].dev;
-
HAOUAS Elyes (Code Review) -
Kyösti Mälkki (Code Review)
-
Patrick Georgi (Code Review)