Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87037?usp=email )
Change subject: soc/mediatek/mt8189: Add DRAM calibration support ......................................................................
soc/mediatek/mt8189: Add DRAM calibration support
Add DRAM calibration support for mt8189. DRAM parameters and related constants are added in dramc_param.h and dramc_soc.h.
The common emi.c can be reused for MT8189 as well, so remove the duplicate mt8189/emi.{c,h}.
Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast calibration via the DRAM blob.
BUG=b:379008996 BRANCH=none TEST=Boot up pass and see log 3200 LPDDR5 chan0(x16) rank0: memory test pass 3200 LPDDR5 chan0(x16) rank1: memory test pass 3200 LPDDR5 chan1(x16) rank0: memory test pass 3200 LPDDR5 chan1(x16) rank1: memory test pass
Signed-off-by: Mike Lin mike.lin@mediatek.corp-partner.google.com Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f Reviewed-on: https://review.coreboot.org/c/coreboot/+/87037 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yidi Lin yidilin@google.com --- M src/soc/mediatek/mt8189/Kconfig M src/soc/mediatek/mt8189/Makefile.mk D src/soc/mediatek/mt8189/emi.c A src/soc/mediatek/mt8189/include/soc/dramc_param.h A src/soc/mediatek/mt8189/include/soc/dramc_soc.h D src/soc/mediatek/mt8189/include/soc/emi.h 6 files changed, 196 insertions(+), 20 deletions(-)
Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig index 512ae54..bf55327 100644 --- a/src/soc/mediatek/mt8189/Kconfig +++ b/src/soc/mediatek/mt8189/Kconfig @@ -8,6 +8,9 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select HAVE_UART_SPECIAL + select CACHE_MRC_SETTINGS + select MEDIATEK_DRAM_BLOB_FAST_INIT + select USE_CBMEM_DRAM_INFO select SOC_MEDIATEK_COMMON select FLASH_DUAL_IO_READ select ARM64_USE_ARCH_TIMER diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index 6774f52..bdee1fb 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -13,15 +13,30 @@ bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
romstage-y += ../common/cbmem.c -romstage-y += emi.c +romstage-y += ../common/dram_init.c +romstage-y += ../common/dramc_param.c +romstage-y += ../common/emi.c +romstage-y += ../common/memory.c ../common/memory_test.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
-ramstage-y += emi.c +ramstage-y += ../common/emi.c +ramstage-y += ../common/memory.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += soc.c ramstage-y += ../common/usb.c usb.c
CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8189_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8189 sf $< $@
diff --git a/src/soc/mediatek/mt8189/emi.c b/src/soc/mediatek/mt8189/emi.c deleted file mode 100644 index 8b933e8..0000000 --- a/src/soc/mediatek/mt8189/emi.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ - -#include <soc/emi.h> - -size_t sdram_size(void) -{ - return (size_t)4 * GiB; -} diff --git a/src/soc/mediatek/mt8189/include/soc/dramc_param.h b/src/soc/mediatek/mt8189/include/soc/dramc_param.h new file mode 100644 index 0000000..719c893 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/dramc_param.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ + +/* + * NOTE: This file is shared between coreboot and dram blob. Any change in this + * file should be synced to the other repository. + */ + +#include <soc/dramc_param_common.h> +#include <soc/dramc_soc.h> +#include <stdint.h> +#include <sys/types.h> + +#define DRAMC_PARAM_HEADER_VERSION 1 +#define CATRAINING_NUM_LP5 7 + +struct sdram_params { + /* rank, cbt */ + u32 rank_num; + u32 dram_cbt_mode; + + u16 delay_cell_timex100; + u8 u18ph_dly[CHANNEL_MAX]; + + /* duty */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP5 + 1]; + s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + + /* cbt */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + u8 cbt_final_range[CHANNEL_MAX][RANK_MAX]; + s16 s2CBTCAWindow_first_pass_Save[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP5]; + s16 s2CBTCAWindow_last_pass_Save[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP5]; + s16 cbt_cmd_dly[CHANNEL_MAX]; + u16 cbt_cs_dly[CHANNEL_MAX]; + u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER]; + + /* write leveling */ + u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* gating */ + u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 wck2dqo_cnt[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* rx input buffer */ + s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP5]; + s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP5]; + + /* tx perbit */ + u16 tx_window_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX]; + s16 u1Txfirst_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 u1Txlast_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][EXT_DQ_DATA_WIDTH]; + u16 wck2dqi_cnt0[CHANNEL_MAX][RANK_MAX]; + u16 wck2dqi_cnt1[CHANNEL_MAX][RANK_MAX]; + + /* rx datlat */ + u8 rx_datlat[CHANNEL_MAX]; + + /* rx perbit */ + u8 rx_best_vref_perbyte[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + //u8 rx_best_vref_perbit[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 u1Rxfirst_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 u1Rxlast_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 rx_perbit_begin; + + /* dvs */ + u8 dvs_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + + u8 perbit_dcc[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + + /* dcm */ + u8 best_u[CHANNEL_MAX][RANK_MAX]; + u8 best_l[CHANNEL_MAX][RANK_MAX]; + + /* Read DCA */ + s8 rdca_u[CHANNEL_MAX][RANK_MAX]; + s8 rdca_l[CHANNEL_MAX][RANK_MAX]; + + /* RDCC */ + s8 rdcc[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* tx oe */ + u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX]; +}; + +struct dramc_data { + struct ddr_base_info ddr_info; + struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; +}; + +struct dramc_param { + struct dramc_param_header header; + void (*do_putc)(unsigned char c); + struct dramc_data dramc_datas; +}; + +#endif /* __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/dramc_soc.h b/src/soc/mediatek/mt8189/include/soc/dramc_soc.h new file mode 100644 index 0000000..0035a90 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/dramc_soc.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ + +#include <soc/dramc_soc_common.h> +#include <stdint.h> + +typedef enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_MAX, +} DRAM_CHANNEL_T; + +typedef enum { + RANK_0 = 0, + RANK_1, + RANK_MAX, +} DRAM_RANK_T; + +typedef enum { + SRAM_SHU0 = 0, + SRAM_SHU1, + SRAM_SHU2, + SRAM_SHU3, + SRAM_SHU4, + DRAM_DFS_SRAM_MAX +} DRAM_DFS_SRAM_SHU_T; /* DRAM SRAM RG type */ + +typedef enum { + DRVP = 0, + DRVN, + ODTN, + IMP_DRV_MAX, +} DRAM_IMP_DRV_T; + +typedef enum { + TYPE_INVALID = 0, + TYPE_DDR1, + TYPE_DDR2, + TYPE_DDR3, + TYPE_DDR4, + TYPE_DDR5, + TYPE_LPDDR2, + TYPE_LPDDR3, + TYPE_PCDDR3, + TYPE_LPDDR4, + TYPE_LPDDR4X, + TYPE_LPDDR4P, + TYPE_LPDDR5, + TYPE_LPDDR5X, + TYPE_MAX, +} DRAM_DRAM_TYPE_T; + +#define DRAM_DFS_SHU_MAX DRAM_DFS_SRAM_MAX +#define DQS_NUMBER_LP5 2 +#define DQ_DATA_WIDTH_LP5 16 +#define EXT_DQ_DATA_WIDTH 18 + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/emi.h b/src/soc/mediatek/mt8189/include/soc/emi.h deleted file mode 100644 index 9f66a7f..0000000 --- a/src/soc/mediatek/mt8189/include/soc/emi.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ - -#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ -#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ - -#include <stddef.h> - -size_t sdram_size(void); - -#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ */
-
Matt DeVillier (Code Review)