Change in coreboot[master]: soc/intel: deduplicate acpi_fill_soc_wake

[Nico Huber (Code Review)]

Attention is currently required from:  Felix Singer, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Duncan Laurie, Michael Niewöhner, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58043 )

Change subject: soc/intel: deduplicate acpi_fill_soc_wake
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Patch Set 3:

(1 comment)

File src/soc/intel/common/block/acpi/acpi.c:

https://review.coreboot.org/c/coreboot/+/58043/comment/05e30957_49ff8bd2 
PS1, Line 220: RTC_EN
> So, *is* RTC alway-on? Doesn't seem to

According to the datasheets it is not. There is still the rumor around that
some bits would be in the wrong power well. I think we should confirm that
for each bit in question before making assumptions.

Even if an EN bit that controls a wake event would be cleared during suspend,
simply assuming it was set won't fix things. It's a bit; if we don't know
what value it had (OS sets the value), chances are 50% to be wrong either
way.

I guess, if this power-well oddity exists at all, the correct way to deal
with it would be to capture the EN state when suspending. (An actual
use-case for GNVS?)