Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39704 )
Change subject: mb/pcengines/apu2: enable PCIe power management features ......................................................................
mb/pcengines/apu2: enable PCIe power management features
Enable ASPM L0s and L1, Common Clock and Clock Power Management for all PCIe ports.
TEST=boot Debian linux and check new PCIe capabilities appear in lspci
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I0a4c83731742f31ab8ef1d326e800dfdc2abb1b7 --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/OemCustomize.c 2 files changed, 19 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/39704/1
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index b434ddc..1915cc2 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -30,6 +30,10 @@ select GENERIC_SPD_BIN select MAINBOARD_HAS_LPC_TPM select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE
config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 6339e0f..e47a2c8 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -33,7 +33,9 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_PORT3_RESET_ID, 0) + AspmL0sL1, + PCIE_PORT3_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -43,7 +45,9 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_NIC_RESET_ID, 0) + AspmL0sL1, + PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -53,7 +57,9 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_NIC_RESET_ID, 0) + AspmL0sL1, + PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -63,7 +69,9 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_NIC_RESET_ID, 0) + AspmL0sL1, + PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -73,7 +81,9 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_GFX_RESET_ID, 0) + AspmL0sL1, + PCIE_GFX_RESET_ID, + ClkPmSupportEnabled) } };
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39704 )
Change subject: mb/pcengines/apu2: enable PCIe power management features ......................................................................
Patch Set 1: Code-Review+2
*sings a lullaby to the PCIe root ports*
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39704 )
Change subject: mb/pcengines/apu2: enable PCIe power management features ......................................................................
Patch Set 1: Code-Review+1
Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39704 )
Change subject: mb/pcengines/apu2: enable PCIe power management features ......................................................................
mb/pcengines/apu2: enable PCIe power management features
Enable ASPM L0s and L1, Common Clock and Clock Power Management for all PCIe ports.
TEST=boot Debian linux and check new PCIe capabilities appear in lspci
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I0a4c83731742f31ab8ef1d326e800dfdc2abb1b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39704 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/OemCustomize.c 2 files changed, 19 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index b434ddc..1915cc2 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -30,6 +30,10 @@ select GENERIC_SPD_BIN select MAINBOARD_HAS_LPC_TPM select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE
config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 6339e0f..e47a2c8 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -33,7 +33,9 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_PORT3_RESET_ID, 0) + AspmL0sL1, + PCIE_PORT3_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -43,7 +45,9 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_NIC_RESET_ID, 0) + AspmL0sL1, + PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -53,7 +57,9 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_NIC_RESET_ID, 0) + AspmL0sL1, + PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -63,7 +69,9 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_NIC_RESET_ID, 0) + AspmL0sL1, + PCIE_NIC_RESET_ID, + ClkPmSupportEnabled) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -73,7 +81,9 @@ HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, PCIE_GFX_RESET_ID, 0) + AspmL0sL1, + PCIE_GFX_RESET_ID, + ClkPmSupportEnabled) } };
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39704 )
Change subject: mb/pcengines/apu2: enable PCIe power management features ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 5/0/5 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1681 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1680 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1679 Non-emulation targets: HP_COMPAQ_8200_ELITE_SFF_PC using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1683 HP_COMPAQ_8200_ELITE_SFF_PC using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1682
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
-
Michał Żygowski (Code Review)
-
Paul Menzel (Code Review)