Change in coreboot[master]: sb/intel/*/smihandler.c: Correct BIOS_CNTL access width

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51939 )

Change subject: sb/intel/*/smihandler.c: Correct BIOS_CNTL access width
......................................................................

sb/intel/*/smihandler.c: Correct BIOS_CNTL access width

The BIOS_CNTL register is 8 bits wide on all affected platforms.

Change-Id: Iaf9267cf27847d54ed50e1f9ae29011d0e99cf8e
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51939
Reviewed-by: Patrick Rudolph 
Tested-by: build bot (Jenkins) 
---
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/lynxpoint/smihandler.c
2 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index 4279eb8..733c625 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -374,7 +374,7 @@
    if (tco_sts & (1 << 8)) { // BIOSWR
    	u8 bios_cntl;

-		bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+		bios_cntl = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xdc);

if (bios_cntl & 1) {
    		/* BWE is RW, so the SMI was caused by a
@@ -388,7 +388,7 @@
    		 * box.
    		 */
    		printk(BIOS_DEBUG, "Switching back to RO\n");
-			pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc,
+			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xdc,
    				(bios_cntl & ~1));
    	} /* No else for now? */
    } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index c2f34ab..9c7b269 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -348,7 +348,7 @@

// BIOSWR
    if (tco_sts & (1 << 8)) {
-		u8 bios_cntl = pci_read_config16(PCH_LPC_DEV, BIOS_CNTL);
+		u8 bios_cntl = pci_read_config8(PCH_LPC_DEV, BIOS_CNTL);

if (bios_cntl & 1) {
    		/*
@@ -362,7 +362,7 @@
    		 * box.
    		 */
    		printk(BIOS_DEBUG, "Switching back to RO\n");
-			pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1));
+			pci_write_config8(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1));
    	} /* No else for now? */
    } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
    	/* Handle TCO timeout */