Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29866 )

Change subject: nb/intel/gm45: Correctly cache TSEG
......................................................................

nb/intel/gm45: Correctly cache TSEG

Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/29866
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/gm45/ram_calc.c
3 files changed, 14 insertions(+), 22 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 95863d9..5373e5e 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -434,7 +434,6 @@
 u32 decode_igd_memory_size(u32 gms);
 u32 decode_igd_gtt_size(u32 gsm);
 u32 decode_tseg_size(u8 esmramc);
-uintptr_t smm_region_start(void);

void init_iommu(void);

diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 0fd7fe5..a001a67 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -221,22 +221,6 @@
    return NULL;
 }

-u32 northbridge_get_tseg_base(void)
-{
-	return (u32)smm_region_start();
-}
-
-u32 northbridge_get_tseg_size(void)
-{
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-
-	if (dev == NULL)
-		die("could not find pci 00:00.0!\n");
-
-	const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);
-	return decode_tseg_size(esmramc) << 10;
-}
-
 void northbridge_write_smram(u8 smram)
 {
    struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 5af3e16..af1a46d 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -26,6 +26,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cbmem.h>
 #include <program_loading.h>
+#include <cpu/intel/smm/gen1/smi.h>
 #include "gm45.h"

/*
@@ -83,7 +84,7 @@
    }
 }

-uintptr_t smm_region_start(void)
+u32 northbridge_get_tseg_base(void)
 {
    const pci_devfn_t dev = PCI_DEV(0, 0, 0);

@@ -106,13 +107,19 @@
    return tor;
 }

+u32 northbridge_get_tseg_size(void)
+{
+	const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
+	return decode_tseg_size(esmramc) << 10;
+}
+
 /* Depending of UMA and TSEG configuration, TSEG might start at any
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
 void *cbmem_top(void)
 {
-	uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB);
+	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
    return (void *) top_of_ram;
 }

@@ -135,12 +142,14 @@
    /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
    postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);

-	/* Cache a 8 MiB region below the top of ram and 8 MiB above top of
+	/* Cache 8 MiB region below the top of ram and 2 MiB above top of
     * ram to cover both cbmem as the TSEG region.
     */
    top_of_ram = (uintptr_t)cbmem_top();
-	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
-			MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+			       MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
+			       northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);

run_postcar_phase(&pcf);