Change in coreboot[master]: amd/stoneyridge: Add ASL helper for AOAC PwrGood Control

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28771

Change subject: amd/stoneyridge: Add ASL helper for AOAC PwrGood Control
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amd/stoneyridge: Add ASL helper for AOAC PwrGood Control

Add a method to assist with setting the PwrGood Control register, which
will be useful for various devices.

BUG=b:77602074

Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
1 file changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28771/1

diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index b8956b4..59daf49 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -639,3 +639,28 @@
    	}
    }
 }
+
+/*
+ * Helper for setting a bit in AOACxA0 PwrGood Control
+ * Arg0 bit location
+ * Arg1 clear or set if Arg0 5, setting exceptions
+ */
+Method(PWGC,2, Serialized)
+{
+	And (PGA3, 0xdf, Local0)  /* do SwUsb3SlpShutdown below */
+	if(Arg1) {
+		Or(Arg0, Local0, Local0)
+	} else {
+		Not(Arg0, Local1)
+		And(Local1, Local0, Local0)
+	}
+	Store(Local0, PGA3)
+	if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */
+		Store(PGA3, Local0)
+		And(Arg0, Local0, Local0)
+		while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */
+			Store(PGA3, Local0)
+			And(Arg0, Local0, Local0)
+		}
+	}
+}