Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 )
Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ......................................................................
Patch Set 8:
(12 comments)
File src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/62498/comment/ade03ec3_3559025f PS3, Line 3: .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
Line removed
Done
https://review.coreboot.org/c/coreboot/+/62498/comment/ad56c84e_e235a1e0 PS3, Line 33: # Acoustic settings
Comment removed
Done
File src/mainboard/clevo/tgl-u/variants/nv40mz/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/62498/comment/fb3e508c_91552bda PS6, Line 3: bootblock-y += gpio.c : : romstage-y += romstage.c : : ramstage-y += gpio.c : ramstage-y += hda_verb.c :
File removed
Done
File src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/62498/comment/0365bb60_8e5770b8 PS6, Line 17: register "external_bypass" = "1"
Looks like both are unpopulated
I expected that :D same on other devices... -> external bypass settings and FIVR settings in the dt can be completely dropped then
https://review.coreboot.org/c/coreboot/+/62498/comment/687128b7_fd48f262 PS6, Line 261: Pantone ROM
Some models ship with a Pantone-validated display. […]
I guess it's not only validated but calibrated and this eeprom probably contains the calibration data
File src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c:
https://review.coreboot.org/c/coreboot/+/62498/comment/81a51f69_f699abc4 PS6, Line 210: PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT),
Changed to `PAD_NC`
Done
File src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62498/comment/0c8ae2e2_296906c6 PS6, Line 9: * Disable AER for the SSD slot to support S0ix with SSDs running : * buggy firmware :
Samsung 980 (non-pro) SSD causes the laptop to fail to wake from s0ix standby while AER is enabled. […]
ouch... Thanks, I'll have to check that on l140mu...
https://review.coreboot.org/c/coreboot/+/62498/comment/fafc0492_a59c792d PS6, Line 12: params->CpuPcieRpAdvancedErrorReporting[0] = 0;
Added both params
Done
File src/mainboard/clevo/tgl-u/variants/nv4x/gpio_early.c:
https://review.coreboot.org/c/coreboot/+/62498/comment/c4dd87fc_24ed29e6 PS3, Line 11: PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, DEEP), /* DGPU_RST#_PCH */ : PAD_CFG_TERM_GPO(GPP_U5, 0, NONE, DEEP), /* DGPU_PWR_EN */
Switched to `PAD_CFG_GPO`
Done
File src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62498/comment/4e818264_32899dc3 PS3, Line 4: # TODO: Check if this is correct
Right, removed the entire power limit config
Done
https://review.coreboot.org/c/coreboot/+/62498/comment/6941e008_c6df18e1 PS3, Line 3: # Power limits : # TODO: Check if this is correct : register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ : .tdp_pl1_override = 10, : .tdp_pl2_override = 20, : }" : register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ : .tdp_pl1_override = 10, : .tdp_pl2_override = 20, : }"
Dropped
Done
https://review.coreboot.org/c/coreboot/+/62498/comment/adce1877_e8aaaa2a PS3, Line 42: register "HybridStorageMode" = "0"
Removed
Done
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Michael Niewöhner (Code Review)