[S] Change in coreboot[master]: soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.h

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73506 )

Change subject: soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.h
......................................................................

soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.h

The bit position of the P state enable bit in the 8 P state MSRs is
identical for all AMD chips including the family 15h model 60h APU that
lives outside of soc/amd. The other bits in those 8 MSRs are more or
less family- and model-specific.

Signed-off-by: Felix Held 
Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77
---
M src/include/cpu/amd/msr.h
M src/soc/amd/cezanne/include/soc/msr.h
M src/soc/amd/common/block/acpi/cpu_power_state.c
M src/soc/amd/glinda/include/soc/msr.h
M src/soc/amd/mendocino/include/soc/msr.h
M src/soc/amd/phoenix/include/soc/msr.h
M src/soc/amd/picasso/include/soc/msr.h
7 files changed, 18 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/73506/1

diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 1fd7ec7..1c1a825 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -41,6 +41,9 @@
 #define PS_STS_REG			0xC0010063
 #define PSTATE_0_MSR			0xC0010064
 #define PSTATE_MSR(pstate)		(PSTATE_0_MSR + (pstate))
+#define  PSTATE_DEF_HI_ENABLE_SHIFT	31
+#define  PSTATE_DEF_HI_ENABLE_MASK	(0x1 << PSTATE_DEF_HI_ENABLE_SHIFT)
+
 #define MSR_PATCH_LOADER		0xC0010020

#define MSR_COFVID_STS			0xC0010071
diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h
index 83357c1..5a0bac1 100644
--- a/src/soc/amd/cezanne/include/soc/msr.h
+++ b/src/soc/amd/cezanne/include/soc/msr.h
@@ -4,8 +4,6 @@
 #define AMD_CEZANNE_MSR_H

/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
-#define PSTATE_DEF_HI_ENABLE_SHIFT	31
-#define PSTATE_DEF_HI_ENABLE_MASK	(0x1 << PSTATE_DEF_HI_ENABLE_SHIFT)
 #define PSTATE_DEF_LO_CUR_DIV_SHIFT	30
 #define PSTATE_DEF_LO_CUR_DIV_MASK	(0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT)
 #define PSTATE_DEF_LO_CUR_VAL_SHIFT	22
diff --git a/src/soc/amd/common/block/acpi/cpu_power_state.c b/src/soc/amd/common/block/acpi/cpu_power_state.c
index 614a715..03f42d7 100644
--- a/src/soc/amd/common/block/acpi/cpu_power_state.c
+++ b/src/soc/amd/common/block/acpi/cpu_power_state.c
@@ -7,7 +7,6 @@
 #include <console/console.h>
 #include <cpu/amd/msr.h>
 #include <cpu/x86/msr.h>
-#include <soc/msr.h>
 #include <types.h>

/*
diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h
index 5500ab5..51ab585 100644
--- a/src/soc/amd/glinda/include/soc/msr.h
+++ b/src/soc/amd/glinda/include/soc/msr.h
@@ -6,8 +6,6 @@
 #define AMD_GLINDA_MSR_H

/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
-#define PSTATE_DEF_HI_ENABLE_SHIFT	31
-#define PSTATE_DEF_HI_ENABLE_MASK	(0x1 << PSTATE_DEF_HI_ENABLE_SHIFT)
 #define PSTATE_DEF_LO_CUR_DIV_SHIFT	30
 #define PSTATE_DEF_LO_CUR_DIV_MASK	(0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT)
 #define PSTATE_DEF_LO_CUR_VAL_SHIFT	22
diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h
index 4b25195..0fe4b6f 100644
--- a/src/soc/amd/mendocino/include/soc/msr.h
+++ b/src/soc/amd/mendocino/include/soc/msr.h
@@ -4,8 +4,6 @@
 #define AMD_MENDOCINO_MSR_H

/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
-#define PSTATE_DEF_HI_ENABLE_SHIFT	31
-#define PSTATE_DEF_HI_ENABLE_MASK	(0x1 << PSTATE_DEF_HI_ENABLE_SHIFT)
 #define PSTATE_DEF_LO_CUR_DIV_SHIFT	30
 #define PSTATE_DEF_LO_CUR_DIV_MASK	(0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT)
 #define PSTATE_DEF_LO_CUR_VAL_SHIFT	22
diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h
index 57001ad..30ac560 100644
--- a/src/soc/amd/phoenix/include/soc/msr.h
+++ b/src/soc/amd/phoenix/include/soc/msr.h
@@ -6,8 +6,6 @@
 #define AMD_PHOENIX_MSR_H

/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
-#define PSTATE_DEF_HI_ENABLE_SHIFT	31
-#define PSTATE_DEF_HI_ENABLE_MASK	(0x1 << PSTATE_DEF_HI_ENABLE_SHIFT)
 #define PSTATE_DEF_LO_CUR_DIV_SHIFT	30
 #define PSTATE_DEF_LO_CUR_DIV_MASK	(0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT)
 #define PSTATE_DEF_LO_CUR_VAL_SHIFT	22
diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h
index ca6b25a..2392614 100644
--- a/src/soc/amd/picasso/include/soc/msr.h
+++ b/src/soc/amd/picasso/include/soc/msr.h
@@ -8,8 +8,6 @@
 #define AMD_PICASSO_MSR_H

/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
-#define PSTATE_DEF_HI_ENABLE_SHIFT	31
-#define PSTATE_DEF_HI_ENABLE_MASK	(0x1 << PSTATE_DEF_HI_ENABLE_SHIFT)
 #define PSTATE_DEF_LO_CUR_DIV_SHIFT	30
 #define PSTATE_DEF_LO_CUR_DIV_MASK	(0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT)
 #define PSTATE_DEF_LO_CUR_VAL_SHIFT	22