Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34904 )
Change subject: mb/asrock/h110m: Add STX variant ......................................................................
mb/asrock/h110m: Add STX variant
Change-Id: If95c7ec78b8bee10ed7ae761754ba7f7d548aa55 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/Kconfig.name M src/mainboard/asrock/h110m/Makefile.inc M src/mainboard/asrock/h110m/bootblock.c M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h110m/include/gpio.h M src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/variants/dvs/gpio.c R src/mainboard/asrock/h110m/variants/dvs/hda_verb.c A src/mainboard/asrock/h110m/variants/dvs/overridetree.cb A src/mainboard/asrock/h110m/variants/stx/gpio.c A src/mainboard/asrock/h110m/variants/stx/hda_verb.c A src/mainboard/asrock/h110m/variants/stx/overridetree.cb 13 files changed, 979 insertions(+), 440 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/34904/1
diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index eebce57..1b4e263 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -1,4 +1,4 @@ -if BOARD_ASROCK_H110M_DVS +if BOARD_ASROCK_H110M_DVS || BOARD_ASROCK_H110M_STX
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,11 +11,13 @@ select INTEL_INT15 select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H + select MAINBOARD_USES_FSP2_0 select GENERIC_SPD_BIN - select SUPERIO_NUVOTON_NCT6791D - select SUPERIO_NUVOTON_NCT6791D_COM_A - select REALTEK_8168_RESET - select RT8168_SET_LED_MODE + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_ASROCK_H110M_STX + select SUPERIO_NUVOTON_NCT6791D if BOARD_ASROCK_H110M_DVS + select SUPERIO_NUVOTON_NCT6791D_COM_A if BOARD_ASROCK_H110M_DVS + select REALTEK_8168_RESET if BOARD_ASROCK_H110M_DVS + select RT8168_SET_LED_MODE if BOARD_ASROCK_H110M_DVS
config IRQ_SLOT_COUNT int @@ -25,9 +27,15 @@ string default "asrock/h110m"
+config VARIANT_DIR + string + default "dvs" if BOARD_ASROCK_H110M_DVS + default "stx" if BOARD_ASROCK_H110M_STX + config MAINBOARD_PART_NUMBER string - default "H110M" + default "H110M-DVS" if BOARD_ASROCK_H110M_DVS + default "H110M-STX" if BOARD_ASROCK_H110M_STX
config MAX_CPUS int @@ -37,6 +45,10 @@ string default "devicetree.cb"
+config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xd00 diff --git a/src/mainboard/asrock/h110m/Kconfig.name b/src/mainboard/asrock/h110m/Kconfig.name index 34c1a3c..c871b62 100644 --- a/src/mainboard/asrock/h110m/Kconfig.name +++ b/src/mainboard/asrock/h110m/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_ASROCK_H110M_DVS bool "H110M-DVS" + +config BOARD_ASROCK_H110M_STX + bool "H110M-STX" diff --git a/src/mainboard/asrock/h110m/Makefile.inc b/src/mainboard/asrock/h110m/Makefile.inc index ce6cf80..be9995e 100644 --- a/src/mainboard/asrock/h110m/Makefile.inc +++ b/src/mainboard/asrock/h110m/Makefile.inc @@ -16,8 +16,10 @@
subdirs-y += spd bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += mainboard.c ramstage-y += ramstage.c -ramstage-y += hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c index 96ce205..d520996 100644 --- a/src/mainboard/asrock/h110m/bootblock.c +++ b/src/mainboard/asrock/h110m/bootblock.c @@ -16,22 +16,28 @@
#include <bootblock_common.h> #include <soc/gpio.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6791d/nct6791d.h> #include "include/gpio.h" +#include <superio/nuvoton/nct6791d/nct6791d.h> +#include <superio/nuvoton/common/nuvoton.h>
static void early_config_superio(void) { - const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); - nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + if (CONFIG(BOARD_ASROCK_H110M_DVS)) { + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } }
static void early_config_gpio(void) { + const struct pad_config *pads; + size_t size; + /* This is a hack for FSP because it does things in MemoryInit() * which it shouldn't do. We have to prepare certain gpios here * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); + pads = get_early_gpio_table(&size); + gpio_configure_pads(pads, size); }
void bootblock_mainboard_init(void) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 3067ffe..9942233 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -145,119 +145,9 @@ }"
register "EnableLan" = "0" - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
register "PmTimerDisabled" = "0"
- # USB - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" - - # SATA - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ - }" - - # PCH UART, SPI, I2C - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoPci, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ - }" - - # Set params for PEG 0:1:0 - register "Peg0MaxLinkWidth" = "Peg0_x16" - # Configure PCIe clockgen in PCH - # PEG0 uses SRCCLKREQ0 and CLKSRC0 - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "0" - register "PcieRpClkSrcNumber[0]" = "0" - - # Enable Root port 6(x1) for LAN. - register "PcieRpEnable[5]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - # Use SRCCLKREQ1# - register "PcieRpClkReqNumber[5]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[5]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[5]" = "1" - # Use CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - # Enable Root port 5 (x1) for PCIE slot. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # Use SRCCLKREQ2# - register "PcieRpClkReqNumber[4]" = "2" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # Use CLK SRC 2 - register "PcieRpClkSrcNumber[4]" = "2" - # Use Hot Plug subsystem - register "PcieRpHotPlug[4]" = "1" - - # Enable Root port 7(x1) for PCIE slot. - register "PcieRpEnable[6]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[6]" = "1" - # Use SRCCLKREQ3# - register "PcieRpClkReqNumber[6]" = "3" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[6]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[6]" = "1" - # Use CLK SRC 3 - register "PcieRpClkSrcNumber[6]" = "3" - # Use Hot Plug subsystem - register "PcieRpHotPlug[6]" = "1" - - # PL2 override 91W - register "tdp_pl2_override" = "91" - # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
@@ -298,13 +188,13 @@ device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.0 off end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 @@ -317,70 +207,7 @@ device pci 1e.4 off end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 off end # SDCard - device pci 1f.0 on # LPC bridge - subsystemid 0x1849 0x1a43 - chip superio/nuvoton/nct6791d - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Parallel - # global - irq 0x1c = 0x10 - irq 0x27 = 0x10 - irq 0x2a = 0x64 - # parallel port - io 0x60 = 0x0378 - irq 0x70 = 7 - drq 0x74 = 4 # No DMA - irq 0xf0 = 0x3c # Printer mode - end - device pnp 2e.2 on # UART A - io 0x60 = 0x03f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # IR - io 0x60 = 0x02f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 KBC - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 1 # Keyboard - irq 0x72 = 12 # Mouse - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6 - device pnp 2e.107 off end # GPIO7 - device pnp 2e.207 off end # GPIO8 - device pnp 2e.8 off end # WDT - device pnp 2e.108 off end # GPIO0 - device pnp 2e.308 off end # GPIO base - device pnp 2e.408 off end # WDTMEM - device pnp 2e.708 off end # GPIO1 - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 off end # GPIO3 - device pnp 2e.209 off end # GPIO4 - device pnp 2e.309 off end # GPIO5 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HWM, LED - io 0x60 = 0x0290 - io 0x62 = 0 - irq 0x70 = 0 - end - device pnp 2e.d off end # BCLK, WDT2, WDT_MEM - device pnp 2e.e off end # CIR wake-up - device pnp 2e.f off end # GPIO PP/OD - device pnp 2e.14 off end # SVID, Port 80 UART - device pnp 2e.16 off end # DS5 - device pnp 2e.116 off end # DS3 - device pnp 2e.316 off end # PCHDSW - device pnp 2e.416 off end # DSWWOPT - device pnp 2e.516 off end # DS3OPT - device pnp 2e.616 off end # DSDSS - device pnp 2e.716 off end # DSPU - end # superio/nuvoton/nct6791d - chip drivers/pc80/tpm - device pnp 4e.0 on end # TPM module - end - end # LPC Interface + device pci 1f.0 on end # Chipset LPC/eSPI Controller device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 4ae9911..4cabfc5 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -13,260 +13,16 @@ * GNU General Public License for more details. */
-#ifndef _GPIO_DVS_H -#define _GPIO_DVS_H +#ifndef _PCH_GPIO_H +#define _PCH_GPIO_H
#include <soc/gpe.h> #include <soc/gpio.h>
-#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ +#define PCH_PAD_CFG(val, config0, config1) \ _PAD_CFG_STRUCT(val, config0, config1)
-/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */ - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ - H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ - /* GPIO Group GPP_B */ - H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ - H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ - H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ - H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ - H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ - /* GPIO Group GPP_C */ - H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ - H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ - H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ - H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ - H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ - /* GPP_C6 - RESERVED */ - /* GPP_C7 - RESERVED */ - H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ - /* GPIO Group GPP_D */ - H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ - H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ - H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ - H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ - H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ - /* GPIO Group GPP_E */ - H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ - H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ - H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ - H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ - /* SATA_DEVSLP0 */ - H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), - /* SATA_DEVSLP1 */ - H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), - /* SATA_DEVSLP2 */ - H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), - H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ - H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ - H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ - H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ - H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ - /* GPIO Group GPP_F */ - H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ - H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ - H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ - H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ - H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ - /* GPIO Group GPP_G */ - H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ - H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ - /* GPIO Group GPP_H */ - H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ - /* GPIO Group GPD */ - H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ - H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ - H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ - H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ - H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ - H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ - H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ - H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ - /* GPIO Group GPP_I */ - H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ - H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ - H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ - H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ - H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ - /* DDPB_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), - /* DDPB_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), - /* DDPC_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), - /* DDPC_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), - /* DDPD_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), - /* DDPD_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), -}; - -/* Early pad configuration in romstage. */ -static const struct pad_config early_gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - /* ---- */ - /* SUSWARN#/SUSPWRDNACK */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ -}; +const struct pad_config *get_gpio_table(size_t *num); +const struct pad_config *get_early_gpio_table(size_t *num);
#endif diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index c93e84c..eab6290 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -19,9 +19,12 @@
void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + const struct pad_config *pads; + size_t size; /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + pads = get_gpio_table(&size); + gpio_configure_pads(pads, size);
params->CdClock = 3; /* Enable Virtual Channel 1 */ diff --git a/src/mainboard/asrock/h110m/variants/dvs/gpio.c b/src/mainboard/asrock/h110m/variants/dvs/gpio.c new file mode 100644 index 0000000..f695d0e --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/gpio.c @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <commonlib/helpers.h> +#include "../../include/gpio.h" + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + PCH_PAD_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + PCH_PAD_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ + PCH_PAD_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + PCH_PAD_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ + PCH_PAD_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ + PCH_PAD_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ + PCH_PAD_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ + PCH_PAD_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ + PCH_PAD_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ + PCH_PAD_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ + PCH_PAD_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ + /* GPIO Group GPP_B */ + PCH_PAD_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ + PCH_PAD_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ + PCH_PAD_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ + PCH_PAD_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ + PCH_PAD_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ + PCH_PAD_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ + PCH_PAD_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ + PCH_PAD_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ + PCH_PAD_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ + PCH_PAD_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ + PCH_PAD_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ + PCH_PAD_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ + PCH_PAD_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ + PCH_PAD_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ + PCH_PAD_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ + PCH_PAD_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ + PCH_PAD_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ + PCH_PAD_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ + PCH_PAD_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ + PCH_PAD_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ + PCH_PAD_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ + PCH_PAD_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ + PCH_PAD_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ + PCH_PAD_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ + /* GPIO Group GPP_C */ + PCH_PAD_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ + PCH_PAD_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ + PCH_PAD_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ + PCH_PAD_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ + PCH_PAD_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ + PCH_PAD_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PCH_PAD_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ + PCH_PAD_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ + PCH_PAD_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ + PCH_PAD_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ + PCH_PAD_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ + PCH_PAD_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ + PCH_PAD_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + PCH_PAD_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ + PCH_PAD_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ + PCH_PAD_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ + PCH_PAD_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ + PCH_PAD_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ + PCH_PAD_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ + PCH_PAD_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ + PCH_PAD_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ + PCH_PAD_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ + /* GPIO Group GPP_D */ + PCH_PAD_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ + PCH_PAD_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ + PCH_PAD_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ + PCH_PAD_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ + PCH_PAD_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ + PCH_PAD_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ + PCH_PAD_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ + PCH_PAD_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ + PCH_PAD_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ + PCH_PAD_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ + PCH_PAD_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ + PCH_PAD_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ + PCH_PAD_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ + PCH_PAD_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ + PCH_PAD_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ + PCH_PAD_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ + PCH_PAD_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ + PCH_PAD_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ + PCH_PAD_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ + PCH_PAD_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ + PCH_PAD_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ + PCH_PAD_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ + PCH_PAD_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ + PCH_PAD_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ + /* GPIO Group GPP_E */ + PCH_PAD_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ + PCH_PAD_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ + PCH_PAD_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ + PCH_PAD_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ + PCH_PAD_CFG(GPP_E4, 0x84000500, 0x0000001c), /* SATA_DEVSLP0 */ + PCH_PAD_CFG(GPP_E5, 0x84000500, 0x0000001d), /* SATA_DEVSLP1 */ + PCH_PAD_CFG(GPP_E6, 0x84000500, 0x0000001e), /* SATA_DEVSLP2 */ + PCH_PAD_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ + PCH_PAD_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + PCH_PAD_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ + PCH_PAD_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ + PCH_PAD_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ + PCH_PAD_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ + /* GPIO Group GPP_F */ + PCH_PAD_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ + PCH_PAD_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ + PCH_PAD_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ + PCH_PAD_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ + PCH_PAD_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ + PCH_PAD_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ + PCH_PAD_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ + PCH_PAD_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ + PCH_PAD_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ + PCH_PAD_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ + PCH_PAD_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ + PCH_PAD_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ + PCH_PAD_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ + PCH_PAD_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ + PCH_PAD_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ + PCH_PAD_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ + PCH_PAD_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ + PCH_PAD_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ + PCH_PAD_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ + PCH_PAD_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ + PCH_PAD_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ + PCH_PAD_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ + PCH_PAD_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ + PCH_PAD_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ + /* GPIO Group GPP_G */ + PCH_PAD_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ + PCH_PAD_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ + PCH_PAD_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ + PCH_PAD_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ + PCH_PAD_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ + PCH_PAD_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ + PCH_PAD_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ + PCH_PAD_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ + PCH_PAD_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ + PCH_PAD_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ + PCH_PAD_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ + PCH_PAD_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ + PCH_PAD_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ + PCH_PAD_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ + PCH_PAD_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ + PCH_PAD_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ + PCH_PAD_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ + PCH_PAD_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ + PCH_PAD_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ + PCH_PAD_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ + PCH_PAD_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ + PCH_PAD_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ + PCH_PAD_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ + PCH_PAD_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ + /* GPIO Group GPP_H */ + PCH_PAD_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ + PCH_PAD_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ + PCH_PAD_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ + PCH_PAD_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ + PCH_PAD_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ + PCH_PAD_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ + PCH_PAD_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ + PCH_PAD_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ + PCH_PAD_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ + PCH_PAD_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ + PCH_PAD_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ + PCH_PAD_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ + PCH_PAD_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ + PCH_PAD_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ + PCH_PAD_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ + PCH_PAD_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ + PCH_PAD_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ + PCH_PAD_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ + PCH_PAD_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ + PCH_PAD_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ + PCH_PAD_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ + PCH_PAD_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ + PCH_PAD_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ + PCH_PAD_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ + /* GPIO Group GPD */ + PCH_PAD_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ + PCH_PAD_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ + PCH_PAD_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ + PCH_PAD_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ + PCH_PAD_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ + PCH_PAD_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ + PCH_PAD_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ + PCH_PAD_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ + PCH_PAD_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ + PCH_PAD_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ + PCH_PAD_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ + PCH_PAD_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ + /* GPIO Group GPP_I */ + PCH_PAD_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ + PCH_PAD_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ + PCH_PAD_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ + PCH_PAD_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ + PCH_PAD_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ + PCH_PAD_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */ + PCH_PAD_CFG(GPP_I6, 0x84000500, 0x00001073), /* DDPB_CTRLDATA */ + PCH_PAD_CFG(GPP_I7, 0x84000500, 0x00000074), /* DDPC_CTRLCLK */ + PCH_PAD_CFG(GPP_I8, 0x84000500, 0x00001075), /* DDPC_CTRLDATA */ + PCH_PAD_CFG(GPP_I9, 0x84000500, 0x00000076), /* DDPD_CTRLCLK */ + PCH_PAD_CFG(GPP_I10, 0x84000500, 0x00001077), /* DDPD_CTRLDATA */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* ---- */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} \ No newline at end of file diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/variants/dvs/hda_verb.c similarity index 100% rename from src/mainboard/asrock/h110m/hda_verb.c rename to src/mainboard/asrock/h110m/variants/dvs/hda_verb.c diff --git a/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb b/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb new file mode 100644 index 0000000..aad1374 --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb @@ -0,0 +1,207 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +chip soc/intel/skylake + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Set params for PEG 0:1:0 + register "Peg0MaxLinkWidth" = "Peg0_x16" + # Configure PCIe clockgen in PCH + # PEG0 uses SRCCLKREQ0 and CLKSRC0 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 6 (x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + # Use SRCCLKREQ1# + register "PcieRpClkReqNumber[5]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 7 (x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 91W + register "tdp_pl2_override" = "91" + + device domain 0 on + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on # Chipset LPC/eSPI Controller + subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct6791d + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + # global + irq 0x1c = 0x10 + irq 0x27 = 0x10 + irq 0x2a = 0x64 + # parallel port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct6791d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + end +end diff --git a/src/mainboard/asrock/h110m/variants/stx/gpio.c b/src/mainboard/asrock/h110m/variants/stx/gpio.c new file mode 100644 index 0000000..472db6c --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/stx/gpio.c @@ -0,0 +1,268 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <commonlib/helpers.h> +#include "../../include/gpio.h" + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPP_A ------- */ + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000000), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003000), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x00003000), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x00003000), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x00003000), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x00000000), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000400, 0x00000000), /* SERIRQ */ + PCH_PAD_CFG(GPP_A7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000000), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001000), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001000), /* CLKOUT_LPC1 */ + PCH_PAD_CFG(GPP_A11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000000), /* SUSWARN#/SUSPWRDNACK */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000000), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003000), /* SUS_ACK# */ + PCH_PAD_CFG(GPP_A16, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A17, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A18, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A19, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A20, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A21, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A23, 0x84000102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_B ------- */ + PCH_PAD_CFG(GPP_B0, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B1, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B2, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B3, 0x44000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B4, 0x84000502, 0x00000000), /* CPU_GP3 */ + PCH_PAD_CFG(GPP_B5, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B6, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B7, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B8, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B9, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B10, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B12, 0x44000600, 0x00000000), /* SLP_S0# */ + PCH_PAD_CFG(GPP_B13, 0x44000600, 0x00000000), /* PLTRST# */ + PCH_PAD_CFG(GPP_B14, 0x84000600, 0x00001000), /* SPKR */ + PCH_PAD_CFG(GPP_B15, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B16, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B17, 0x44000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B18, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B19, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B20, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B22, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B23, 0x84000a01, 0x00001000), /* PCHHOT# */ + /* ------- GPIO Group GPP_C ------- */ + PCH_PAD_CFG(GPP_C0, 0x44000502, 0x00000000), /* SMBCLK */ + PCH_PAD_CFG(GPP_C1, 0x44000502, 0x00000000), /* SMBDATA */ + PCH_PAD_CFG(GPP_C2, 0x44000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C3, 0x44000502, 0x00000000), /* SML0CLK */ + PCH_PAD_CFG(GPP_C4, 0x44000502, 0x00000000), /* SML0DATA */ + PCH_PAD_CFG(GPP_C5, 0x84000100, 0x00000000), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PCH_PAD_CFG(GPP_C8, 0x84000502, 0x00000000), /* UART0_RXD */ + PCH_PAD_CFG(GPP_C9, 0x84000600, 0x00000000), /* UART0_TXD */ + PCH_PAD_CFG(GPP_C10, 0x84000600, 0x00000000), /* UART0_RTS# */ + PCH_PAD_CFG(GPP_C11, 0x84000502, 0x00000000), /* UART0_CTS# */ + PCH_PAD_CFG(GPP_C12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C13, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C14, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C15, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C16, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C17, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C18, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C19, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C20, 0x84000502, 0x00000000), /* UART2_RXD */ + PCH_PAD_CFG(GPP_C21, 0x84000600, 0x00000000), /* UART2_TXD */ + PCH_PAD_CFG(GPP_C22, 0x84000600, 0x00000000), /* UART2_RTS# */ + PCH_PAD_CFG(GPP_C23, 0x40880102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_D ------- */ + PCH_PAD_CFG(GPP_D0, 0xc4000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D1, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D2, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D3, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D4, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D5, 0x84000402, 0x00000000), /* I2S_SFRM */ + PCH_PAD_CFG(GPP_D6, 0x84000600, 0x00000000), /* I2S_TXD */ + PCH_PAD_CFG(GPP_D7, 0x84000502, 0x00000000), /* I2S_RXD */ + PCH_PAD_CFG(GPP_D8, 0x84000402, 0x00000000), /* I2S_SCLK */ + PCH_PAD_CFG(GPP_D9, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D10, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D13, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D14, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D15, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D16, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D17, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D18, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D19, 0x84000500, 0x00003000), /* DMIC_CLK0 */ + PCH_PAD_CFG(GPP_D20, 0x84000500, 0x00003000), /* DMIC_DATA0 */ + PCH_PAD_CFG(GPP_D21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D23, 0x84000102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_E ------- */ + PCH_PAD_CFG(GPP_E0, 0x84000502, 0x00003000), /* SATAXPCIE0 */ + PCH_PAD_CFG(GPP_E1, 0x84000502, 0x00003000), /* SATAXPCIE1 */ + PCH_PAD_CFG(GPP_E2, 0x84000502, 0x00003000), /* SATAXPCIE2 */ + PCH_PAD_CFG(GPP_E3, 0x84000502, 0x00000000), /* CPU_GP0 */ + PCH_PAD_CFG(GPP_E4, 0x84000500, 0x00000000), /* SATA_DEVSLP0 */ + PCH_PAD_CFG(GPP_E5, 0x84000500, 0x00000000), /* SATA_DEVSLP1 */ + PCH_PAD_CFG(GPP_E6, 0x84000500, 0x00000000), /* SATA_DEVSLP2 */ + PCH_PAD_CFG(GPP_E7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_E8, 0x84000600, 0x00000000), /* SATA_LED# */ + PCH_PAD_CFG(GPP_E9, 0x44000502, 0x00000000), /* USB_OC0# */ + PCH_PAD_CFG(GPP_E10, 0x44000502, 0x00000000), /* USB_OC1# */ + PCH_PAD_CFG(GPP_E11, 0x44000502, 0x00000000), /* USB_OC2# */ + PCH_PAD_CFG(GPP_E12, 0x44000502, 0x00000000), /* USB_OC3# */ + /* ------- GPIO Group GPP_F ------- */ + PCH_PAD_CFG(GPP_F0, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F1, 0x84000502, 0x00003000), /* SATAXPCIE4 */ + PCH_PAD_CFG(GPP_F2, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F3, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F4, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F5, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F6, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F8, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F9, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F10, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F12, 0x80900102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F13, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F14, 0x40900102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F15, 0x44000502, 0x00000000), /* USB_OC4# */ + PCH_PAD_CFG(GPP_F16, 0x44000502, 0x00000000), /* USB_OC5# */ + PCH_PAD_CFG(GPP_F17, 0x44000502, 0x00000000), /* USB_OC6# */ + PCH_PAD_CFG(GPP_F18, 0x84000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F19, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F20, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F21, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F23, 0x84000100, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_G ------- */ + PCH_PAD_CFG(GPP_G0, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G1, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G2, 0x80800102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G3, 0x80800102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G4, 0x44000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G5, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G6, 0x80800102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G7, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G8, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G9, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G10, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G13, 0x84000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G14, 0x80800100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G15, 0x84000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G16, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G17, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G18, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G19, 0x84000500, 0x00000000), /* SMI# */ + PCH_PAD_CFG(GPP_G20, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G23, 0x84000102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_H ------- */ + PCH_PAD_CFG(GPP_H0, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H1, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H2, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H3, 0x44000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H4, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H5, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H6, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H7, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H8, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H9, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H10, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H11, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H12, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H13, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H14, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H15, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H16, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H17, 0x84000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H18, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H19, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H20, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H23, 0x04000102, 0x00000000), /* GPIO */ + /* -------- GPIO Group GPD -------- */ + PCH_PAD_CFG(GPD0, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD1, 0x04000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD2, 0x00080602, 0x00003c00), /* LAN_WAKE# */ + PCH_PAD_CFG(GPD3, 0x04000502, 0x00003000), /* PWRBTN# */ + PCH_PAD_CFG(GPD4, 0x04000600, 0x00000000), /* SLP_S3# */ + PCH_PAD_CFG(GPD5, 0x04000600, 0x00000000), /* SLP_S4# */ + PCH_PAD_CFG(GPD6, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD7, 0x84000103, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD8, 0x04000600, 0x00000000), /* SUSCLK */ + PCH_PAD_CFG(GPD9, 0x04000600, 0x00000000), /* SLP_WLAN# */ + PCH_PAD_CFG(GPD10, 0x04000600, 0x00000000), /* SLP_S5# */ + PCH_PAD_CFG(GPD11, 0x04000600, 0x00000000), /* LANPHYPC */ + /* ------- GPIO Group GPP_I ------- */ + PCH_PAD_CFG(GPP_I0, 0x84000500, 0x00000000), /* DDPB_HPD0 */ + PCH_PAD_CFG(GPP_I1, 0x84000502, 0x00000000), /* DDPC_HPD1 */ + PCH_PAD_CFG(GPP_I2, 0x84000502, 0x00000000), /* DDPD_HPD2 */ + PCH_PAD_CFG(GPP_I3, 0x84000500, 0x00000000), /* DDPE_HPD3 */ + PCH_PAD_CFG(GPP_I4, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_I5, 0x84000502, 0x00000000), /* DDPB_CTRLCLK */ + PCH_PAD_CFG(GPP_I6, 0x84000502, 0x00001000), /* DDPB_CTRLDATA */ + PCH_PAD_CFG(GPP_I7, 0x84000500, 0x00000000), /* DDPC_CTRLCLK */ + PCH_PAD_CFG(GPP_I8, 0x84000500, 0x00001000), /* DDPC_CTRLDATA */ + PCH_PAD_CFG(GPP_I9, 0x84000500, 0x00000000), /* DDPD_CTRLCLK */ + PCH_PAD_CFG(GPP_I10, 0x84000500, 0x00001000), /* DDPD_CTRLDATA */ +}; + +/* Early pad configuration in romstage */ +static const struct pad_config early_gpio_table[] = { + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000000), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003000), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x00003000), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x00003000), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x00003000), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x00000000), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000400, 0x00000000), /* SERIRQ */ + PCH_PAD_CFG(GPP_A7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000000), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001000), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001000), /* CLKOUT_LPC1 */ + PCH_PAD_CFG(GPP_A11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000000), /* SUSWARN#/SUSPWRDNACK */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000000), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003000), /* SUS_ACK# */ +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/asrock/h110m/variants/stx/hda_verb.c b/src/mainboard/asrock/h110m/variants/stx/hda_verb.c new file mode 100644 index 0000000..52e3039 --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/stx/hda_verb.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki naresh.solanki@intel.com for Intel Corp.) + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* ALC283 coreboot specific header */ + 0x10ec0283, /* Codec Vendor / Device ID: Realtek */ + 0x18491283, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x18491283), + AZALIA_PIN_CFG(0x0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1a, 0x02a19020), + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40559c05), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x21, 0x0221101f), + + /* Intel Kaby Lake HDA coreboot specific header */ + 0x8086280b, /* Codec Vendor / Device ID */ + 0x80860101, + 0x00000004, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x2, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/h110m/variants/stx/overridetree.cb b/src/mainboard/asrock/h110m/variants/stx/overridetree.cb new file mode 100644 index 0000000..45403c8 --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/stx/overridetree.cb @@ -0,0 +1,133 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +chip soc/intel/skylake + + # FSP Configuration + register "EnableLan" = "1" + + # USB 2.0 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port Front Panel + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port Front Panel + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" # USB3/2 Type A Front Panel + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" # USB3/2 Type A Back panel + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # USB3/2 Type A Back panel + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + register "usb2_ports[10]" = "USB2_PORT_EMPTY" + register "usb2_ports[11]" = "USB2_PORT_EMPTY" + register "usb2_ports[12]" = "USB2_PORT_EMPTY" + register "usb2_ports[13]" = "USB2_PORT_EMPTY" + + # USB 3.0 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A Front Panel + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A Back panel + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A Back panel + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + register "usb3_ports[6]" = "USB3_PORT_EMPTY" + register "usb3_ports[7]" = "USB3_PORT_EMPTY" + register "usb3_ports[8]" = "USB3_PORT_EMPTY" + register "usb3_ports[9]" = "USB3_PORT_EMPTY" + + # SATA + # SATA0 - Unused + # SATA1 - Bottom left connector + # SATA2 - Bottom right connector + # SATA3 - Top side connector + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 0, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # PEG 0:1:0 is used for NVMe x4 2280 M.2 + register "Peg0MaxLinkWidth" = "Peg0_x4" + # Configure PCH PCIe clockgen for PEG0: SRCCLKREQ7 and CLKSRC7 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "7" + register "PcieRpClkSrcNumber[0]" = "7" + + # Root port 4 (x1) is used for I219V LAN device + register "PcieRpEnable[3]" = "1" + # Use SRCCLKREQ13 and CLKSRC10 + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "13" + register "PcieRpClkSrcNumber[3]" = "10" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[3]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[3]" = "1" + + # Root port 7(x1) is used for 2242 M.2 PCIE slot + register "PcieRpEnable[6]" = "1" + # Use SRCCLKREQ1 and CLKSRC1 + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "1" + register "PcieRpClkSrcNumber[6]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 65W + register "tdp_pl2_override" = "65" + + device domain 0 on + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on # Chipset LPC/eSPI Controller + subsystemid 0x1849 0x1a43 + end # LPC Interface + end +end
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34904 )
Change subject: mb/asrock/h110m: Add STX variant ......................................................................
Patch Set 4:
(3 comments)
Patch Set 4:
(4 comments)
Thanks for the review
https://review.coreboot.org/c/coreboot/+/34904/4/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/Kconfig:
https://review.coreboot.org/c/coreboot/+/34904/4/src/mainboard/asrock/h110m/... PS4, Line 17: BOARD_ASROCK_H110M_DVS
Doesn't the H110M-STX use a NCT6791D as well?
No, this board uses NCT5567D
https://review.coreboot.org/c/coreboot/+/34904/4/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/bootblock.c:
https://review.coreboot.org/c/coreboot/+/34904/4/src/mainboard/asrock/h110m/... PS4, Line 25: if (CONFIG(BOARD_ASROCK_H110M_DVS)) {
I would suggest changing the if condition: https://github. […]
This is a temporary solution. The board has a Nuvoton nct5567D . If I am not mistaken, then this chip has the same registers as the NCT5539D, https://review.coreboot.org/c/coreboot/+/33842
https://review.coreboot.org/c/coreboot/+/34904/4/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/variants/dvs/overridetree.cb:
PS4:
You would want to rebase this change atop the ones that change this devicetree
Yes, but first, I should to fix device tree for the dvs variant
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Maxim Polyakov (Code Review)