Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Subrata Banik (Code Review)]

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Paul Menzel, Meera Ravindranath, Angel Pons.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )

Change subject: mb/adlrvp: Fix DDR5 Boot issue
......................................................................

Patch Set 13:

(1 comment)

File src/mainboard/intel/adlrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/50996/comment/15a7ea55_f0aca572 
PS13, Line 60: ADL_P_DDR5_2
> Here you are skipping the call to `memcfg_init()`. […]

@meera, can you please address this review comment ?

Consider to move this in below file?https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/mem...

void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
    	 const struct mem_spd *spd_info, bool half_populated)
{
    static const int spd_array[] = { 0xA0, 0xA2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xA4, 0xA6,
    0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }

switch (mb_cfg->type) {
    case MEM_TYPE_DDR5:
           /* Fill FSP UPDs with SMBus Addresses until SMbus driver in coreboot
       is updated with DDR5 support
       TODO: Drop this check once the SMBus driver is ready */
       for (int i = 0; i < 16; i++)
    	m_cfg->SpdAddressTable[i] = spd_array[i];     
    case MEM_TYPE_DDR4:
    	meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
    	dq_dqs_auto_detect = true;
    	break;
         ....
    }
that way you are not skipping anything important?