Change in coreboot[master]: src/soc/tigerlake: Enabled D3HotEnable in fsp_params - coreboot-gerrit

9 Mar 2020


      Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39368 )
Change subject: src/soc/tigerlake: Enabled D3HotEnable in fsp_params
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39368/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39368/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 162: params->D3HotEnable = 1;
...
Also, I believe the EDS exposes the registers for setting these bits. […]
how about we move D3HotEnable and D3ColdEnable into the device
tree and set these whenever we enable TcssXhciEn in the device
tree?
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/39368
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iaba12339378b38ff850da812135f51a1d8d4130f
Gerrit-Change-Number: 39368
Gerrit-PatchSet: 3
Gerrit-Owner: Caveh Jalali caveh@chromium.org
Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com
Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.corp-partner.google.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Furquan Shaikh furquan@google.com
Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-CC: Wonkyu Kim wonkyu.kim@intel.com
Gerrit-Comment-Date: Tue, 10 Mar 2020 04:03:18 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Furquan Shaikh furquan@google.com
Gerrit-MessageType: comment