Change in ...coreboot[master]: mb/google/sarien/variants: Add DPTF based charge control

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30723

Change subject: mb/google/sarien/variants: Add DPTF based charge control
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mb/google/sarien/variants: Add DPTF based charge control

Add DPTF based input chargning current throttling based on temperature.

BRANCH=None
BUG=b:122483425
TEST=Built for sarien

Change-Id: If01fea731926ec29ca5a0595b875acce9b1f5a2f
Signed-off-by: Sumeet Pawnikar 
---
M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
2 files changed, 18 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/30723/1

diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
index 2d35878..8f8cde5 100644
--- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
@@ -27,7 +27,15 @@
 #define DPTF_TSR1_CRITICAL	80

#undef DPTF_ENABLE_FAN_CONTROL
-#undef DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },  /* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },  /* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },   /* 0.5A */
+})

Name (DTRT, Package () {
    /* CPU Throttle Effect on CPU */
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
index 2d35878..8f8cde5 100644
--- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
@@ -27,7 +27,15 @@
 #define DPTF_TSR1_CRITICAL	80

#undef DPTF_ENABLE_FAN_CONTROL
-#undef DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },  /* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },  /* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },   /* 0.5A */
+})

Name (DTRT, Package () {
    /* CPU Throttle Effect on CPU */

[S] Change in coreboot[master]: mb/google/sarien/variants: Add DPTF based charge control

[Stefan Reinauer (Code Review)]

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30723?usp=email )

Change subject: mb/google/sarien/variants: Add DPTF based charge control
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Abandoned