Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
Attention is currently required from: Nico Huber, Patrick Rudolph, Benjamin Doron, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50754 )
Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ......................................................................
Patch Set 3:
(4 comments)
File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/50754/comment/c84a0283_3d3c5dcb PS1, Line 398: fast_spi_enable_wp
I can't find that document. Is it public? […]
Ack
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/50754/comment/da1308c1_bbbe9507 PS1, Line 363: if (fast_spi_wpd_status()) {
if possible you shouldn't touch wpd in this commit at all. only reset the SMI status bits to prevent SMI storm.
Done
https://review.coreboot.org/c/coreboot/+/50754/comment/f4c41a4f_56060dbf PS1, Line 368: uint16_t bios_cntl = pci_read_config16(PCH_DEV_LPC, 0xdc);
Regarding LPC, even if CB:40830 doesn't enable protection, I guess it doesn't hurt to handle BIOSWR_ […]
eSPI is not handled in this patch. I don't have a board with eSPI to test things on and the SOC_ESPI Kconfig option is specific to APL.
https://review.coreboot.org/c/coreboot/+/50754/comment/f2b78e68_9371c5a5 PS1, Line 368: PCH_DEV_LPC
SPI_SYNC_SS clearing (discussed above) must also be done on eSPI (but not LPC). […]
eSPI is not handled in this patch. (see above comment for reasoning)
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Angel Pons (Code Review)