Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63552 )

Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
......................................................................

mb/google/brya: Reset XHCI controller while preparing for S5

This patch calls into `xhci_host_reset()` function to perform XHCI
controller reset.

BUG=b:227289581
TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7)
during resume from S5.

Total Time: 1,045,855
localhost ~ # cbmem -c | grep ERROR

No PMC timeout error is observed with this CL.

Signed-off-by: Subrata Banik 
Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149
---
M src/mainboard/google/brya/smihandler.c
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/63552/1

diff --git a/src/mainboard/google/brya/smihandler.c b/src/mainboard/google/brya/smihandler.c
index 9208d51..19fed79 100644
--- a/src/mainboard/google/brya/smihandler.c
+++ b/src/mainboard/google/brya/smihandler.c
@@ -1,15 +1,20 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

+#include <acpi/acpi.h>
 #include <cpu/x86/smm.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/smm.h>
 #include <elog.h>
 #include <intelblocks/smihandler.h>
+#include <intelblocks/xhci.h>
 #include <variant/ec.h>

void mainboard_smi_sleep(u8 slp_typ)
 {
    chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
+	/* USB sleep preparations */
+	if (slp_typ == ACPI_S5)
+		xhci_host_reset();
 }

int mainboard_smi_apmc(u8 apmc)