Attention is currently required from: Marc Jones, Nico Huber, Ryback Hung, Johnny Lin, Paul Menzel, Tim Wawrzynczak, Shuming Chu (Shuming).
Wilson Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67264 )
Change subject: device: Clear lane error status ......................................................................
Patch Set 3:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67264/comment/9742ce70_2355b4f8 PS2, Line 2: Author: WilsonChou3333 Wilson.Chou@quantatw.com
git config --global user.name "Wilson Chou" […]
Done
https://review.coreboot.org/c/coreboot/+/67264/comment/e8c6107b_4ee9fd3e PS2, Line 7: src/
`src/` is not needed.
Done
https://review.coreboot.org/c/coreboot/+/67264/comment/d07f2cc3_694e157c PS2, Line 11: , to
Maybe end the sentence with a dot/period, and start a new one.
Done
https://review.coreboot.org/c/coreboot/+/67264/comment/2e539fb0_f55333f7 PS2, Line 12: clear
clears
Done
https://review.coreboot.org/c/coreboot/+/67264/comment/16d5fc75_d07f325a PS2, Line 13: reqgister
register
Done
https://review.coreboot.org/c/coreboot/+/67264/comment/e825afe5_29303911 PS2, Line 21:
What was shown before?
It happens randomly. If it records an error, it will show Capabilities: [a30 v1] Secondary PCI Express LnkCtl3: LnkEquIntrruptEn- PerformEqu- LaneErrStat: LaneErr at lane: 5
https://review.coreboot.org/c/coreboot/+/67264/comment/a5e39130_9ed4e078 PS2, Line 22: WilsonChou3333
Wilson Chou
Done
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Wilson Chou (Code Review)