Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15011
-gerrit
commit 2dbce7217a6b8a89f9b161e1881331d75b983440 Author: Lee Leahy leroy.p.leahy@intel.com Date: Thu May 26 17:12:17 2016 -0700
Add Board Checklist Support
Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required).
Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented
TEST=Build with Galileo Gen2.
Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- Makefile.inc | 182 +++++++++++++++++++++ src/Kconfig | 8 + src/drivers/intel/fsp1_1/Kconfig | 4 + .../fsp/fsp1_1/checklist/bootblock_complete.dat | 77 +++++++++ .../fsp/fsp1_1/checklist/ramstage_complete.dat | 53 ++++++ .../fsp/fsp1_1/checklist/ramstage_optional.dat | 46 ++++++ .../fsp/fsp1_1/checklist/romstage_complete.dat | 54 ++++++ .../fsp/fsp1_1/checklist/romstage_optional.dat | 34 ++++ .../fsp/fsp1_1/checklist/verstage_complete.dat | 35 ++++ .../fsp/fsp1_1/checklist/verstage_optional.dat | 22 +++ 10 files changed, 515 insertions(+)
diff --git a/Makefile.inc b/Makefile.inc index 574f2fe..2d2405e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -559,6 +559,188 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug mv $@.tmp $@
########################################################################### +# Build the board implementation checklist +########################################################################### + +%.symbols: %.elf + echo $@ + # + # All symbols in the image + # + nm $< | sed -r 's/^.{11}//' > $@ + +%.weak: %.elf + echo $@ + # + # Weak symbols in the image + # + nm $< | fgrep " W " | sed -r 's/^.{11}//' > $@ + +%.expected: %.elf + echo $@ + # + # Expected symbols in the image + # + cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_complete.dat $@.tmp + # If no separate verstage, combine verstage and romstage routines into a single list + if [ ! -e $(*D)/verstage.elf ]; \ + then \ + if [ "$(*F)" = "romstage" ]; \ + then \ + cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_complete.dat >> $@.tmp; \ + fi; \ + fi + sort $@.tmp > $@.tmp2 + sort -u $@.tmp2 > $@ + rm $@.tmp $@.tmp2 + +%.optional: %.elf + echo $@ + # + # Optional symbols in the image + # + cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat $@.tmp + # If no separate verstage, combine verstage and romstage routines into a single list + if [ ! -e $(*D)/verstage.elf ]; \ + then \ + if [ "$(*F)" = "romstage" ]; \ + then \ + cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_optional.dat >> $@.tmp; \ + fi; \ + fi + sort $@.tmp > $@.tmp2 + sort -u $@.tmp2 > $@ + rm $@.tmp $@.tmp2 + +%.done: %.symbols %.expected %.weak %.optional + echo $@ + # + # Expected Symbols Optional Weak Done Type + # no yes no d/c yes Don't display + # yes no no no no Required - not implemented + # yes no yes no no Optional - not implemented + # yes yes yes yes no Optional - not implemented + # yes yes no no yes Required - implemented + # yes yes yes no yes Required - implemented + # + # Implemented routines are in the symbol table and are not weak + # + comm -12 $(*D)/$(*F).expected $(*D)/$(*F).symbols | sed "s/^[ \t]*//" > $@.tmp + comm -23 $@.tmp $(*D)/$(*F).weak | sed "s/^[ \t]*//" > $@ + rm $@.tmp + +%.optional2: %.optional %.done + echo $@ + # + # Remove any routines that are implemented + # + comm -23 $^ | sed "s/^[ \t]*//" > $@ + +%.tbd: %.expected %.done %.optional2 + echo $@ + # + # Remove any implemented or optional routines + # + comm -23 $(*D)/$(*F).expected $(*D)/$(*F).done | sed "s/^[ \t]*//" > $@.tmp + comm -23 $@.tmp $(*D)/$(*F).optional2 | sed "s/^[ \t]*//" > $@ + rm $@.tmp + +# Count the lines in the done file +done_lines = $$(wc -l $(*D)/$(basename $(*F)).done | sed 's/ .*//') + +# Count the lines in the optional file +optional_lines = $$(wc -l $(*D)/$(basename $(*F)).optional2 | sed 's/ .*//') + +# Count the lines in the expected file +expected_lines = $$(wc -l $(*D)/$(basename $(*F)).expected | sed 's/ .*//') + +# Compute the percentage done by routine count +percent_complete = $$(($(done_lines) * 100 / ($(expected_lines) - $(optional_lines)))) + +# Build the implementation table for each stage +%.html: %.optional2 %.done %.expected %.tbd + # + # Done table rows are in green + # + sed -e 's/^/<tr bgcolor=#c0ffc0><td>Required</td><td>/' $(*D)/$(basename $(*F)).done > $@.tmp + # + # Optional table rows are in yellow + # + sed -e 's/^/<tr bgcolor=#ffffc0><td>Optional</td><td>/' $(*D)/$(basename $(*F)).optional2 >> $@.tmp + # + # TBD table rows are in red + # + if [ -s $(*D)/$(basename $(*F)).tbd ]; \ + then \ + sed -e 's/^/<tr bgcolor=#ffc0c0><td>Required</td><td>/' $(*D)/$(basename $(*F)).tbd >> $@.tmp; \ + fi + # + # Add the table row termination + # + sed -e 's/$$/</td></tr>/' -i $@.tmp + # + # Sort the table into alphabetical order + # + sort -t ">" -k4 $@.tmp > $@.tmp2 + # + # Build the table + # + echo "<table border=1>" > $@ + echo "<tr><th colspan=2>$(basename $(*F)): $(percent_complete)% Done</th></tr>" >> $@ + echo "<tr><th>Type</th><th>Routine</td></tr>" >> $@ + cat $@.tmp2 >> $@ + echo "</table>" >> $@ + echo "<br>" >> $@ + rm $@.tmp $@.tmp2 + +html_table_files = $(objcbfs)/romstage.html $(objcbfs)/ramstage.html +list_of_html_files = $(subst _NEWLINE_,${\n},${html_table_files}) +current_date = $$(date +"%Y/%m/%d") + +# Build the web page from the implementation tables +$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(html_table_files) + # + # Add the header to the web page + # + echo "<html>" > $@ + echo "<head>" >> $@ + echo "<title>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status</title>" >> $@ + echo "</title>" >> $@ + echo "<body>" >> $@ + echo "<h1>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status: $(current_date)</h1>" >> $@ + # + # Add the tables to the web page + # + for table in $(list_of_html_files); do \ + cat $$table >> $@; \ + done + # + # Add the trailer to the web page + # + echo "</body>" >> $@ + echo "</html>" >> $@ + +Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR) ]; \ + then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR); \ + fi + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board ]; \ + then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board; \ + fi + cp $< $@ + +# Only build the checklist for boards under development +ifeq ($(CONFIG_CREATE_BOARD_CHECKLIST),y) +ifeq ($(CONFIG_MAKE_CHECKLIST_PUBLIC),y) +INTERMEDIATE+=Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +else +INTERMEDIATE+=$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +endif +endif + +########################################################################### # Build the final rom image ###########################################################################
diff --git a/src/Kconfig b/src/Kconfig index f93c2cc..2b9a136 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1175,3 +1175,11 @@ config DEBUG_BOOT_STATE help Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. + +config CREATE_BOARD_CHECKLIST + bool + default n + +config MAKE_CHECKLIST_PUBLIC + bool + default n diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 9b2c463..86f6c7b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -115,4 +115,8 @@ config VBT_FILE depends on GOP_SUPPORT default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin"
+config CHECKLIST_DATA_FILE_LOCATION + string + default "src/vendorcode/intel/fsp/fsp1_1/checklist" + endif #PLATFORM_USES_FSP1_1 diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat new file mode 100644 index 0000000..8a4325f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat @@ -0,0 +1,77 @@ +arch_segment_loaded +backup_top_of_ram +bootblock_mainboard_early_init +bootblock_mainboard_init +bootblock_soc_early_init +bootblock_soc_init +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fill_power_state +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_memory_init_params +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +mrc_cache_get_current +mrc_cache_stash_data +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +raminit +ramstage_cache_invalid +report_memory_config +save_chromeos_gpios +setup_stack_and_mtrrs +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_ram_init +soc_after_silicon_init +soc_display_memory_init_params +soc_display_silicon_init_params +soc_fill_acpi_wake +soc_memory_init_params +soc_pre_ram_init +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +timestamp_tick_freq_mhz +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat new file mode 100644 index 0000000..64f8584 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat @@ -0,0 +1,53 @@ +acpi_create_serialio_ssdt +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_io_trap_handler +mainboard_post +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_silicon_init +soc_display_silicon_init_params +soc_fill_acpi_wake +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +timestamp_tick_freq_mhz +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat new file mode 100644 index 0000000..6608583 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat @@ -0,0 +1,46 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_io_trap_handler +mainboard_post +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_silicon_init +soc_display_silicon_init_params +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat new file mode 100644 index 0000000..e6bef6c --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat @@ -0,0 +1,54 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fill_power_state +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_fill_spd_data +mainboard_io_trap_handler +mainboard_memory_init_params +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +migrate_power_state +mrc_cache_get_current_with_version +mrc_cache_stash_data_with_version +platform_prog_run +platform_segment_loaded +print_fsp_info +raminit +ramstage_cache_invalid +report_memory_config +romstage_common +save_chromeos_gpios +set_max_freq +setup_stack_and_mtrrs +smm_region +smm_region_size +soc_after_ram_init +soc_display_memory_init_params +soc_display_mtrrs +soc_get_variable_mtrr_count +soc_memory_init_params +soc_pre_ram_init +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat new file mode 100644 index 0000000..2634566 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat @@ -0,0 +1,34 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +soc_after_ram_init +soc_display_memory_init_params +soc_display_mtrrs +soc_get_variable_mtrr_count +soc_memory_init_params +soc_pre_ram_init +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat new file mode 100644 index 0000000..2124f0f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat @@ -0,0 +1,35 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +get_sw_write_protect_state +gpio_acpi_path +init_timer +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_post +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +soc_display_mtrrs +soc_get_variable_mtrr_count +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat new file mode 100644 index 0000000..f589eaa --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat @@ -0,0 +1,22 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +soc_display_mtrrs +soc_get_variable_mtrr_count +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init
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Leroy P Leahy