Change in coreboot[master]: sb/amd/sb700/bootblock.c: Refactor configure ROM function

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62103 )

Change subject: sb/amd/sb700/bootblock.c: Refactor configure ROM function
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sb/amd/sb700/bootblock.c: Refactor configure ROM function

Signed-off-by: Michał Żygowski 
Change-Id: Iff4f30399f713f2fe1e00d4b4a9d50641b5bc2e2
---
M src/southbridge/amd/sb700/bootblock.c
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/62103/1

diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index dd80ba2..d575207 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -16,6 +16,7 @@

#include <stdint.h>
 #include <arch/bootblock.h>
+#include <arch/mmio.h>
 #include <device/pci_ops.h>

#define IO_MEM_PORT_DECODE_ENABLE_5	0x48
@@ -107,16 +108,15 @@

/* Temporarily set up SPI access to change SPI speed */
    	prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS);
-		dword &= ~(0x7ffffff << 5);		/* SPI_BaseAddr */
-		dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5);
-		dword |= (0x1 << 1);			/* SpiRomEnable = 1 */
+		dword &= ~0xffffffe0;		/* SPI_BaseAddr */
+		dword |= TEMPORARY_SPI_BASE_ADDRESS;
+		dword |= BIT(1);		/* SpiRomEnable = 1 */
    	pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword);

-		spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
-		dword = *spi_mmio;
+		dword = read32(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
    	dword &= ~(0x3 << 12);	/* NormSpeed = 0x1 */
    	dword |= (0x1 << 12);
-		*spi_mmio = dword;
+		write32(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1, dword);

/* Restore previous SPI access */
    	pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);