Change in coreboot[master]: amd/padmelon: Fix up PCIe settings

[John E. Kabat (Code Review)]

Hello Marshall Dawson,

I'd like you to do a code review. Please visit

https://review.coreboot.org/21039

to review the following change.

Change subject: amd/padmelon: Fix up PCIe settings
......................................................................

amd/padmelon: Fix up PCIe settings

Change devicetree.cb and OemCustomize.c to match the board's
design.  This has been checked with a Merlin Falcon APU.  Brown
Falcon supports only 4 Gfx lanes.

Add the missing PSP device to the devicetree, remove the
extraneous "hudson" HDA device, and move the two "kern" HDAs
to northbridge (see "root complex" diagram in the BKDG).

Change-Id: Id638c2bc980d5d2bfb4d49290fa24b9869543814
Signed-off-by: Marshall Dawson 
---
M src/mainboard/amd/padmelon/OemCustomize.c
M src/mainboard/amd/padmelon/devicetree.cb
2 files changed, 21 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/21039/1

diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c
index 3d1d20c..9ed7e42 100644
--- a/src/mainboard/amd/padmelon/OemCustomize.c
+++ b/src/mainboard/amd/padmelon/OemCustomize.c
@@ -31,7 +31,7 @@
    			AspmDisabled, 0x02, 0)
    },

-	/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+	/* Initialize Port descriptor (PCIe port, Lane 7, PCI Device Number 2, ...) */
    {
    	0,
    	PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
@@ -41,30 +41,30 @@
    			PcieGenMaxSupported,
    			AspmDisabled, 0x03, 0)
    },
-	/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+	/* Initialize Port descriptor (PCIe port, Lane 6, PCI Device Number 2, ...) */
    {
    	0,
-		PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 4,
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
    			HotplugDisabled,
    			PcieGenMaxSupported,
    			PcieGenMaxSupported,
    			AspmDisabled, 0x04, 0)
    },
-	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */
+	/* Initialize Port descriptor (PCIe port, Lane 5, PCI Device Number 2, ...) */
    {
    	0,
    	PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
+		PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 3,
    			HotplugDisabled,
    			PcieGenMaxSupported,
    			PcieGenMaxSupported,
-				AspmDisabled, 0x05, 0)
+				AspmDisabled, 0x04, 0)
    },
-	/* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */
+	/* Initialize Port descriptor (PCIe port, Lane4, PCI Device Number 2, ...) */
    {
    	0,
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
    	PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
    			HotplugDisabled,
    			PcieGenMaxSupported,
@@ -74,8 +74,8 @@
    /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */
    {
    	DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags  !!!IMPORTANT!!! Terminate last element of array */
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+		PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 1,
    			HotplugDisabled,
    			PcieGenMaxSupported,
    			PcieGenMaxSupported,
diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb
index 2b6171a..1902311 100644
--- a/src/mainboard/amd/padmelon/devicetree.cb
+++ b/src/mainboard/amd/padmelon/devicetree.cb
@@ -28,18 +28,19 @@
    			device pci 1.0 on  end # Internal Graphics P2P bridge 0x9804
    			device pci 1.1 on  end # Internal Multimedia
    			device pci 2.0 on  end # PCIe Host Bridge
-				device pci 2.1 on  end # x4 PCIe slot
-				device pci 2.2 on  end # mPCIe slot
-				device pci 2.3 on  end # Realtek NIC
-				device pci 2.4 on  end # Edge Connector
-				device pci 2.5 on  end # Edge Connector
-				device pci 3.0 on  end # Edge Connector
-				device pci 3.1 on  end # Edge Connector
+				device pci 2.1 off end # No x4 PCIe slot
+				device pci 2.2 on  end # Half mPCIe slot
+				device pci 2.3 off end # NC
+				device pci 2.4 on  end # RTL8111F
+				device pci 2.5 on  end # RTL8111F
+				device pci 3.0 on  end # PCIe Host Bridge
+				device pci 3.1 on  end # x8 slot (x4 with Brown Falcon)
+				device pci 8.0 off end # PSP
+				device pci 9.0 on  end # HDA
+				device pci 9.2 on  end # HDA
    		end	#chip northbridge/amd/pi/00660F01

chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
-				device pci 9.0 on  end # HDA
-				device pci 9.2 on  end # HDA
    			device pci 10.0 on  end # USB
    			device pci 11.0 on  end # SATA
    			device pci 12.0 on  end # USB
@@ -51,7 +52,6 @@
    					device i2c 52 on end
    				end
    			end # SM
-				#device pci 14.2 on  end # HDA	0x4383
    			device pci 14.3 on      # LPC	0x439d
    				chip superio/fintek/f81803a
    					register "conf_key_mode" = "0x77"