Change in coreboot[master]: cpu/intel/common: implement the two missing CPPC v2 autonomous registers

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46463 )

Change subject: cpu/intel/common: implement the two missing CPPC v2 autonomous registers
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cpu/intel/common: implement the two missing CPPC v2 autonomous registers

This implements the two missing registers for the CPPC Hardware
Autonomous mode (HWP) to the CPPC v2 package.

The right values can be determined via Intel SDM and the ACPI 6.3 spec.

Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled
version

Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Paul Menzel 
Reviewed-by: Matt Delco 
---
M src/cpu/intel/common/common_init.c
1 file changed, 16 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Matt Delco: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index d0b66d4..3ea8f36 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -239,11 +239,23 @@
    if (version >= 2) {
    	/* Autonomous Selection Enable is populated below */

-		/* Autonomous Activity Window Register */
-		config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported;
+		msr.addrl = IA32_HWP_REQUEST;

-		/* Energy Performance Preference Register */
-		config->regs[CPPC_PERF_PREF] = unsupported;
+		/*
+		 * Autonomous Activity Window Register
+		 * ResourceTemplate(){Register(FFixedHW, 0x0a, 0x20, 0x774, 0x04,)},
+		 */
+		msr.bit_width = 10;
+		msr.bit_offset = 32;
+		config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = msr;
+
+		/*
+		 * Autonomous Energy Performance Preference Register
+		 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x774, 0x04,)},
+		 */
+		msr.bit_width = 8;
+		msr.bit_offset = 24;
+		config->regs[CPPC_PERF_PREF] = msr;

/* Reference Performance */
    	config->regs[CPPC_REF_PERF] = unsupported;