Change in coreboot[master]: nb/intel/x4x: Use postcar stage to tear down CAR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26716

Change subject: nb/intel/x4x: Use postcar stage to tear down CAR
......................................................................

nb/intel/x4x: Use postcar stage to tear down CAR

Change-Id: I4c5c5648fd6e54e61f2bd532624331cdd0d52ece
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/car/cache_as_ram_ht.inc
M src/cpu/intel/socket_LGA775/Makefile.inc
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/Makefile.inc
M src/northbridge/intel/x4x/ram_calc.c
5 files changed, 14 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/26716/1

diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 0eb58d1..5f2a91a 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -348,6 +348,10 @@
    post_code(0x2f)
    /* Call romstage.c main function. */
    call	romstage_main
+#if IS_ENABLED(CONFIG_POSTCAR_STAGE)
+	/* Should never be reached */
+	jmp	.Lhlt
+#endif
    /* Save return value from romstage_main. It contains the stack to use
     * after cache-as-ram is torn down. It also contains the information
     * for setting up MTRRs. */
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
index ffcd1cb..78a2f32 100644
--- a/src/cpu/intel/socket_LGA775/Makefile.inc
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -14,5 +14,5 @@
 subdirs-y += ../speedstep

cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-romstage-y += ../car/romstage.c
+postcar-$(CONFIG_POSTCAR_STAGE) += ../car/teardown_car.S
 romstage-y += ../car/romstage.c
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index d9dbdc9..610f785 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -29,6 +29,8 @@
    select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
    select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
    select CACHE_MRC_SETTINGS
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE

config CBFS_SIZE
    hex
diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc
index 1f7e483..3118b09 100644
--- a/src/northbridge/intel/x4x/Makefile.inc
+++ b/src/northbridge/intel/x4x/Makefile.inc
@@ -29,4 +29,6 @@
 ramstage-y += gma.c
 ramstage-y += northbridge.c

+postcar-y += ram_calc.c
+
 endif
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 1009372..b5efabe 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -103,8 +103,6 @@
    return (void *) top_of_ram;
 }

-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
 /* setup_stack_and_mtrrs() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mtrrs(void)
@@ -112,7 +110,7 @@
    struct postcar_frame pcf;
    uintptr_t top_of_ram;

-	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+	if (postcar_frame_init(&pcf, 1*KiB))
    	die("Unable to initialize postcar frame.\n");

/* Cache the ROM as WP just below 4GiB. */
@@ -131,8 +129,8 @@
    postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
    postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);

-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs.
-	 */
-	return postcar_commit_mtrrs(&pcf);
+	run_postcar_phase(&pcf);
+
+	/* We don't return here */
+	return NULL;
 }