Change in coreboot[master]: soc/intel/skylake: Drop FSP_CAR options

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29533

Change subject: soc/intel/skylake: Drop FSP_CAR options
......................................................................

soc/intel/skylake: Drop FSP_CAR options

It's not implemented for Skylake, all combinations that try to enable it
either result in Kconfig or linker errors.

Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's
effective.

TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default
     configs with and without this patch: binaries stay the same.

Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28
Signed-off-by: Nico Huber 
---
M src/drivers/intel/fsp1_1/Kconfig
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/romstage/romstage.c
3 files changed, 10 insertions(+), 36 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29533/1

diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index a70f00d..8054021 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -104,4 +104,9 @@
    bool "Reset the system on S3 wake when ramstage cache invalid."
    default n

+config SKIP_FSP_CAR
+	def_bool n
+	help
+	  Selected by platforms that implement their own CAR setup.
+
 endif #PLATFORM_USES_FSP1_1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 1449d3d..e5a60f6 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -34,6 +34,7 @@
    select INTEL_DESCRIPTOR_MODE_CAPABLE
    select HAVE_MONOTONIC_TIMER
    select HAVE_SMI_HANDLER
+	select INTEL_CAR_NEM_ENHANCED
    select INTEL_GMA_ACPI
    select IOAPIC
    select MRC_SETTINGS_PROTECT
@@ -54,6 +55,7 @@
    select SOC_INTEL_COMMON
    select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
    select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_CAR
    select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
    select SOC_INTEL_COMMON_BLOCK_CPU
    select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
@@ -100,6 +102,7 @@
    depends on !MAINBOARD_USES_FSP2_0
    select PLATFORM_USES_FSP1_1
    select DISPLAY_FSP_ENTRY_POINTS
+	select SKIP_FSP_CAR

config CHROMEOS
    select CHROMEOS_RAMOOPS_DYNAMIC
@@ -276,32 +279,6 @@
    help
      Include DSP firmware settings for DA7219 headset codec.

-choice
-	prompt "Cache-as-ram implementation"
-	default USE_SKYLAKE_CAR_NEM_ENHANCED
-	help
-	  This option allows you to select how cache-as-ram (CAR) is set up.
-
-config USE_SKYLAKE_CAR_NEM_ENHANCED
-	bool "Enhanced Non-evict mode"
-	select SOC_INTEL_COMMON_BLOCK_CAR
-	select INTEL_CAR_NEM_ENHANCED
-	help
-	  A current limitation of NEM (Non-Evict mode) is that code and data
-	  sizes are derived from the requirement to not write out any modified
-	  cache line. With NEM, if there is no physical memory behind the
-	  cached area, the modified data will be lost and NEM results will be
-	  inconsistent. ENHANCED NEM guarantees that modified data is always
-	  kept in cache while clean data is replaced.
-
-config USE_SKYLAKE_FSP_CAR
-	bool "Use FSP CAR"
-	select FSP_CAR
-	help
-	  Use FSP APIs to initialize and tear down the Cache-As-Ram.
-
-endchoice
-
 config FSP_HEADER_PATH
    string "Location of FSP headers"
    depends on MAINBOARD_USES_FSP2_0
@@ -316,12 +293,6 @@
    default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE
    default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE

-config SKIP_FSP_CAR
-	bool "Skip cache as RAM setup in FSP"
-	default y
-	help
-	  Skip Cache as RAM setup in FSP.
-
 config SPI_FLASH_INCLUDE_ALL_DRIVERS
    bool
    default n
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 215b07c..4eedb96 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -85,10 +85,8 @@
    	upd->SaGv = config->SaGv;
    upd->RMT = config->Rmt;
    upd->DdrFreqLimit = config->DdrFreqLimit;
-	if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) {
-		upd->FspCarBase = CONFIG_DCACHE_RAM_BASE;
-		upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE;
-	}
+	upd->FspCarBase = CONFIG_DCACHE_RAM_BASE;
+	upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE;
 }

void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,