Attention is currently required from: Chen, Gang C.
Hello Chen, Gang C,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/81322?usp=email
to review the following change.
Change subject: mainboard/intel: Add Beechnut City CRB initial support ......................................................................
mainboard/intel: Add Beechnut City CRB initial support
configs/builder/config.intel.crb.bnc is introduced as the defconfig file for the new board target.
Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Signed-off-by: Shuo Liu shuo.liu@intel.com Signed-off-by: Gang Chen gang.c.chen@intel.com --- A configs/builder/config.intel.crb.bnc A src/mainboard/intel/beechnutcity_crb/Kconfig A src/mainboard/intel/beechnutcity_crb/Kconfig.name A src/mainboard/intel/beechnutcity_crb/Makefile.inc A src/mainboard/intel/beechnutcity_crb/board.fmd A src/mainboard/intel/beechnutcity_crb/board_info.txt A src/mainboard/intel/beechnutcity_crb/bootblock.c A src/mainboard/intel/beechnutcity_crb/devicetree.cb A src/mainboard/intel/beechnutcity_crb/dsdt.asl A src/mainboard/intel/beechnutcity_crb/include/config/iio.h A src/mainboard/intel/beechnutcity_crb/ramstage.c A src/mainboard/intel/beechnutcity_crb/romstage.c 12 files changed, 279 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81322/1
diff --git a/configs/builder/config.intel.crb.bnc b/configs/builder/config.intel.crb.bnc new file mode 100644 index 0000000..8b82d1c --- /dev/null +++ b/configs/builder/config.intel.crb.bnc @@ -0,0 +1,51 @@ +# Type this in coreboot root directory to get a working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.bnc + +# +# [RO] Board Configurations +# +CONFIG_VENDOR_INTEL=y +CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB=y + +CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y +CONFIG_CONFIGURABLE_RAMSTAGE=y + +CONFIG_NO_GFX_INIT=y + +CONFIG_HAVE_IFD_BIN=y +CONFIG_VALIDATE_INTEL_DESCRIPTOR=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_LINUX=y + +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_CONSOLE_SERIAL_115200=y + +# +# [RW] IFWI Ingredients +# +CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin" +CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb" +CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd" +CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/" + +CONFIG_PAYLOAD_FILE="site-local/beechnutcity/linuxboot_bzImage" +CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200" + +# +# [RW] Debug Settings +# +CONFIG_CONSOLE_POST=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y + +CONFIG_VERIFY_HOBS=y +CONFIG_DISPLAY_MTRRS=y + +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y + +CONFIG_HAVE_DEBUG_GPIO=y +CONFIG_DEBUG_GPIO=y diff --git a/src/mainboard/intel/beechnutcity_crb/Kconfig b/src/mainboard/intel/beechnutcity_crb/Kconfig new file mode 100644 index 0000000..f71a1c1 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Kconfig @@ -0,0 +1,35 @@ +if BOARD_INTEL_BEECHNUTCITY_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_GRANITERAPIDS + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select VPD + select MEMORY_MAPPED_TPM + +config MAINBOARD_DIR + string + default "intel/beechnutcity_crb" + +config MAINBOARD_PART_NUMBER + string + default "Beechnut City CRB" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config ASPEED_SIO_PORT + hex + default 0x2E + +config DIMM_MAX + int + default 1 + +endif diff --git a/src/mainboard/intel/beechnutcity_crb/Kconfig.name b/src/mainboard/intel/beechnutcity_crb/Kconfig.name new file mode 100644 index 0000000..895d160 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_BEECHNUTCITY_CRB + bool "Beechnut City CRB" diff --git a/src/mainboard/intel/beechnutcity_crb/Makefile.inc b/src/mainboard/intel/beechnutcity_crb/Makefile.inc new file mode 100644 index 0000000..4c7a7be --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += ramstage.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/beechnutcity_crb/board.fmd b/src/mainboard/intel/beechnutcity_crb/board.fmd new file mode 100644 index 0000000..435bda3 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/board.fmd @@ -0,0 +1,11 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x03000000 { + SI_DESC@0x0 0x1000 + } + + RW_MRC_CACHE@0x3000000 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) +} diff --git a/src/mainboard/intel/beechnutcity_crb/board_info.txt b/src/mainboard/intel/beechnutcity_crb/board_info.txt new file mode 100644 index 0000000..1de903e --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Beechnut City CRB +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/beechnutcity_crb/bootblock.c b/src/mainboard/intel/beechnutcity_crb/bootblock.c new file mode 100644 index 0000000..966f33d --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/bootblock.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <soc/pci_devs.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +void bootblock_mainboard_early_init(void) +{ + /* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + lpc_io_setup_comm_a_b(); + lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F); + + if (CONFIG_UART_FOR_CONSOLE == 0) { + /* Setup superio com1 */ + const pnp_devfn_t serial_dev = PNP_DEV(CONFIG_ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } else + die("COMs other than COM1 not supported\n"); +} diff --git a/src/mainboard/intel/beechnutcity_crb/devicetree.cb b/src/mainboard/intel/beechnutcity_crb/devicetree.cb new file mode 100644 index 0000000..b1c75de --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/devicetree.cb @@ -0,0 +1,54 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/gnr + + # configure VT-d + register "vtd_support" = "1" + register "x2apic" = "1" + + # configure LPC generic IO decode ranges + # [bits 31..24: reserved] + # [bits 23..18: io decode address mask <7..2>] + # [bits 17..16: reserved] + # [bits 15..2 : io decode dword aligned address <15..2>] + # [bit 1 : reserved] + # [bit 0 : enabled] + register "gen1_dec" = "0x00000CA1" # IPMI KCS + register "gen2_dec" = "0x0" + register "gen3_dec" = "0x0" + register "gen4_dec" = "0x0" + + # configure FSP debug settings + register "serial_io_uart_debug_io_base" = "0x3F8" + + # configure BIOS lockdown + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_FSP, + }" + + # configure devices + device cpu_cluster 0 on end + + device domain 0 on + device pci 00.0 mandatory end # MMAP/VT-d + device gpio 0 alias ibl_gpio_communities on end # GPIO + device mmio 0xfed00000 on end # HEPT + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 # PNP_IDX_IO0 + irq 0x70 = 4 # PNP_IDX_IRQ0 + end + end + end + end + chip drivers/ipmi + device pnp ca2.0 on end # BMC KCS + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + end + end + +end diff --git a/src/mainboard/intel/beechnutcity_crb/dsdt.asl b/src/mainboard/intel/beechnutcity_crb/dsdt.asl new file mode 100644 index 0000000..246dc99 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/dsdt.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/gnr/acpi/gpe.asl> + #include <soc/intel/xeon_sp/gnr/acpi/platform.asl> + #include <commonlib/include/commonlib/console/post_codes.h> + #include <arch/x86/acpi/post.asl> + #include <arch/x86/acpi/debug.asl> +} diff --git a/src/mainboard/intel/beechnutcity_crb/include/config/iio.h b/src/mainboard/intel/beechnutcity_crb/include/config/iio.h new file mode 100644 index 0000000..8a52f56 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/include/config/iio.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _BOARD_CONFIG_IIO_H_ +#define _BOARD_CONFIG_IIO_H_ + +#include <soc/iio.h> + +static const iio_pe_config bnc_iio_config_table[] = { + _IIO_PE_CFG_STRUCT_BEGIN(0x0, PE0, IIO_BIFURCATE_x2x2x2x2x8, PE_TYPE_PCIE) { + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x2), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x3), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x4), + _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x5) + } _IIO_PE_CFG_STRUCT_END, +}; + +#endif /* _BOARD_CONFIG_IIO_H_ */ diff --git a/src/mainboard/intel/beechnutcity_crb/ramstage.c b/src/mainboard/intel/beechnutcity_crb/ramstage.c new file mode 100644 index 0000000..8d31628 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + return; +} diff --git a/src/mainboard/intel/beechnutcity_crb/romstage.c b/src/mainboard/intel/beechnutcity_crb/romstage.c new file mode 100644 index 0000000..8e65af4 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <console/console.h> +#include <drivers/ipmi/ipmi_if.h> +#include <drivers/vpd/vpd.h> +#include <soc/iio.h> +#include <soc/ddr.h> +#include <soc/romstage.h> + +#include "config/iio.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* Early connect BMC, e.g. to query configuration parameters */ + if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n", + CONFIG_BMC_KCS_BASE); + + /* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */ + if (CONFIG_BIOS_SIZE) { + mupd->FspmConfig.BiosRegionBase = BASE_4GB - CONFIG_BIOS_SIZE; + mupd->FspmConfig.BiosRegionSize = CONFIG_BIOS_SIZE; + printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase); + printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize); + } else { + printk(BIOS_ERR, "BIOS_SIZE is not set!!!\n"); + } + + /* IIO init */ + soc_config_iio_pe_ports(mupd, bnc_iio_config_table, + sizeof(bnc_iio_config_table)/sizeof(iio_pe_config)); + +} + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) +{ + return false; +}
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Shuo Liu (Code Review)