Change in coreboot[master]: soc/intel/elkhartlake: Enable PCH GBE

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Angel Pons, Lean Sheng Tan, Werner Zeh.
Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55355

to look at the new patch set (#24).

Change subject: soc/intel/elkhartlake: Enable PCH GBE
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soc/intel/elkhartlake: Enable PCH GBE

Enable PCH GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Use EHL own GBE ACPI instead of common code version due to
   different B:D.F from the usual GBE
3. Add kconfig PMC_EPOC to use the PMC XTAL read function

Due to EHL GBE comes with time sensitive networking (TSN)
capability integrated, EHL FSP is using 'PchTsn' instead of the
usual 'PchLan' naming convention across the board.

Signed-off-by: Lean Sheng Tan 
Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f
---
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/acpi/southbridge.asl
A src/soc/intel/elkhartlake/acpi/tsn_glan.asl
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/fsp_params.c
6 files changed, 72 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/55355/24