Change in coreboot[master]: soc/intel/skylake: Set PsysPl3 and Pl4

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/23527

Change subject: soc/intel/skylake: Set PsysPl3 and Pl4
......................................................................

soc/intel/skylake: Set PsysPl3 and Pl4

If given a value for PsysPl3 and/or Pl4, set the
appropriate MSR.

BUG=b:71594855
BRANCH=None
TEST=boot up and check MSRs in OS to make sure values are
     set as expected.

Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed
Signed-off-by: Shelley Chen 
---
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/include/soc/msr.h
4 files changed, 39 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/23527/1

diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 45f201c..7aa81f0 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -114,6 +114,8 @@
 #define PKG_POWER_LIMIT_CLAMP		(1 << 16)
 #define PKG_POWER_LIMIT_TIME_SHIFT	17
 #define PKG_POWER_LIMIT_TIME_MASK	(0x7f)
+#define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24
+#define PKG_POWER_LIMIT_DUTYCYCLE_MASK  (0x7f)
 /* SMM save state MSRs */
 #define SMBASE_MSR			0xc20
 #define IEDBASE_MSR			0xc22
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 4e8cb81..6568701 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -100,6 +100,12 @@
    /* SysPL2 Value in Watts */
    u32 tdp_psyspl2;

+	/* SysPL3 Value in Watts */
+	u32 tdp_psyspl3;
+
+	/* PL4 Value in Watts */
+	u32 tdp_pl4;
+
    /*
     * The following fields come from FspUpdVpd.h.
     * These are configuration values that are passed to FSP during
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 291a40d..f3da826 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -191,6 +191,36 @@
    	wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
    }

+	/* Set PsysPl3 */
+	if (conf->tdp_psyspl3) {
+		limit = rdmsr(MSR_PL3_CONTROL);
+		limit.lo = 0;
+		printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n",
+		       conf->tdp_psyspl3);
+		limit.lo |= (conf->tdp_psyspl3 * power_unit) &
+			PKG_POWER_LIMIT_MASK;
+		/* Enable PsysPl3 */
+		limit.lo |= PKG_POWER_LIMIT_EN;
+		/* set max possible time window */
+		limit.lo |= PKG_POWER_LIMIT_TIME_MASK <<
+			PKG_POWER_LIMIT_TIME_SHIFT;
+		/* set minimum duty cycle */
+		limit.lo |= PKG_POWER_LIMIT_DUTYCYCLE_MASK <<
+			PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;
+		wrmsr(MSR_PL3_CONTROL, limit);
+	}
+
+	/* Set Pl4 */
+	if (conf->tdp_pl4) {
+		limit = rdmsr(MSR_VR_CURRENT_CONFIG);
+		limit.lo = 0;
+		printk(BIOS_DEBUG, "CPU PsysPL4 = %u Watts\n",
+		       conf->tdp_pl4);
+		limit.lo |= (conf->tdp_pl4 * power_unit) &
+			PKG_POWER_LIMIT_MASK;
+		wrmsr(MSR_VR_CURRENT_CONFIG, limit);
+	}
+
    /* Set DDR RAPL power limit by copying from MMIO to MSR */
    msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
    msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index 0bd7f3c..780f94f 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -36,6 +36,7 @@
 #define MSR_UNCORE_PRMRR_PHYS_MASK	0x2f5
 #define MSR_VR_CURRENT_CONFIG		0x601
 #define MSR_VR_MISC_CONFIG		0x603
+#define MSR_PL3_CONTROL                 0x615
 #define MSR_VR_MISC_CONFIG2		0x636
 #define MSR_PP0_POWER_LIMIT		0x638
 #define MSR_PP1_POWER_LIMIT		0x640