Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e --- A Documentation/mainboard/ocp/deltalake.md 1 file changed, 98 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42947/1
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md new file mode 100644 index 0000000..3af893a --- /dev/null +++ b/Documentation/mainboard/ocp/deltalake.md @@ -0,0 +1,98 @@ +# OCP Delta Lake + +This page describes coreboot support status for the [OCP] (Open Compute Project) +Delta Lake server platform. + +## Introduction + +OCP Delta Lake server platform is a component of multi-host server system +Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020]. + +Delta Lake server is a one socket CooperLake Sacalable Processor server. + +Yosemite-V3 has multiple configurations. Depending on configurations, it may +host up to 4 Delta Lake servers in one sled. + +Yosemite-V3 and Delta Lake are currently in DVT phase. Facebook, Intel and partners +jointly develop FSP/coreboot/Linuxboot solution on Delta Lake as a hack project. + +## Required blobs + +This board currently requires: +- FSP blob: The blob (Intel CooperLake Scalable Processor Firmware Support Package) + is not yet available to the public. It will be made public some time after the MP + of CooperLake Scalable Processor when the FSP is mature. +- Microcode: Not yet available to the public. +- ME binary: Not yet available to the public. + +## Payload +- Linuxboot: This is necessary only if you use Linuxboot as coreboot payload. + U-root as initramfs, is used in the joint development. It can be built + following [All about u-root]. + +## Flashing coreboot + +To do in-band FW image update, use [flashrom]: + flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \ + -i bios --noverify-all -w <path to coreboot image> + +From OpenBMC, to update FW image: + fw-util slotx --update bios <path to coreboot image> + +To power off/on the host: + power-util slotx off + power-util slotx on + +To connect to console through SOL (Serial Over Lan): + sol-util slotx + +## Working features +The solution is developed using Linuxboot payload. The Linuxboot +kernel versions tried is 5.2.9. The initramfs image is u-root. +- Most SMBIOS types +- BMC integration: + - BMC readiness check + - IPMI commands + - watchdog timer + - POST complete pin acknowledgement +- SEL record generation +- Early serial output +- port 80h direct to GPIO +- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT +- Skipping memory training upon subsequent reboots +- BMC crash dump +- Error injection through ITP + +## Firmware configurations +[ChromeOS VPD] is used to store most of firmware configurations. RO_VPD +holds default values, while RW_VPD holds customized values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses its value to populate smbios type 1 version field. + +## Known issues / feature gaps +- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not + support FSP_USES_CB_STACK. An IPS ticket is filed with Intel. +- VT-d is not supported. An IPS ticket is filed with Intel. +- PCIe bifuration is not supported. An IPS ticket is filed with Intel. +- SMBIOS type 7 and type 17 are not populated. +- ME based power capping. + +## Technology + +```eval_rst ++------------------------+---------------------------------------------+ +| Processor (1 socket) | Intel CooperLake Scalable Processor | ++------------------------+---------------------------------------------+ +| BMC | Aspeed AST 2500 | ++------------------------+---------------------------------------------+ +| PCH | Intel Lewisburg C621 | ++------------------------+---------------------------------------------+ +``` + +[OCP]: https://www.opencompute.org +[OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule +[flashrom]: https://flashrom.org/Flashrom +[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root +[ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 1:
(7 comments)
Exciting stuff!
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 17: jointly develop FSP/coreboot/Linuxboot solution on Delta Lake as a hack project. I'd like a better word than hack. In fact, I would remove "as a hack project" words entirely.
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 51: kernel versions tried is 5.2.9. The initramfs image is u-root. version
is it worth adding u-root.org as a pointer when you mention u-root.
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 62: - Skipping memory training upon subsequent reboots fantastic.
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 67: [ChromeOS VPD] is used to store most of firmware configurations. RO_VPD most of the firmware configurations.
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 80: - ME based power capping. capping is ... what? not supported? ticket filed? Never will be supported?
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 88: | BMC | Aspeed AST 2500 | complete with the embedded well known password :-)?
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 94: [OCP]: https://www.opencompute.org nice links!
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 1:
(6 comments)
Thanks for the review!
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 51: kernel versions tried is 5.2.9. The initramfs image is u-root.
version […]
Done
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 62: - Skipping memory training upon subsequent reboots
fantastic.
Done
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 67: [ChromeOS VPD] is used to store most of firmware configurations. RO_VPD
most of the firmware configurations.
Done
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 80: - ME based power capping.
capping is ... […]
This is a bug in ME. Filed ticket with Intel ME team. Will update the text.
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 88: | BMC | Aspeed AST 2500 |
complete with the embedded well known password :-)?
I am sorry, I am not sure I understand the comment and what needs to be changed.
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 94: [OCP]: https://www.opencompute.org
nice links!
Done
Hello Philipp Deppenwiese, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Rudolph, Ryback Hung, Johnny Lin, Paul Menzel, Christian Walter, Angel Pons, Morgan Jang, Bryant Ou, Ron Minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42947
to look at the new patch set (#2).
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e --- A Documentation/mainboard/ocp/deltalake.md 1 file changed, 106 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42947/2
ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 2: Code-Review+1
(15 comments)
Thank you for the writing this. I noticed some minor things.
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 11: CooperLake Cooper Lake
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 17: Linuxboot LinuxBoot
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 22: CooperLake Cooper Lake
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 23: MP What is MP?
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 29: Linuxboot LinuxBoot
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 29: Linuxboot LinuxBoot
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 50: Linuxboot LinuxBoot
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 50: The solution is developed using Linuxboot payload. The Linuxboot : kernel versions tried is 5.2.9. The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root] as initramfs.
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 51: versions version
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 62: - Skipping memory training upon subsequent reboots … by using MRC cache.
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 73: its that
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 78: - VT-d is not supported. An IPS ticket is filed with Intel. I thought Linux can set that up.
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 81: with Intel. Use two spaces for consistency instead of tab?
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 86: that so
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 93: CooperLake Cooper Lake
ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 23: MP
What is MP?
Mass Production I believe, it's a standard term of art.
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 78: - VT-d is not supported. An IPS ticket is filed with Intel.
I thought Linux can set that up.
very good point. It would be nice to know more about this problem. What has to be done that linux can not do?
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 2:
(13 comments)
Thanks!
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 11: CooperLake
Cooper Lake
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 17: Linuxboot
LinuxBoot
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 22: CooperLake
Cooper Lake
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 23: MP
Mass Production I believe, it's a standard term of art.
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 29: Linuxboot
LinuxBoot
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 29: Linuxboot
LinuxBoot
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 50: Linuxboot
LinuxBoot
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 51: versions
version
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 50: The solution is developed using Linuxboot payload. The Linuxboot : kernel versions tried is 5.2.9.
The solution is developed using LinuxBoot payload with Linux kernel 5.2. […]
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 62: - Skipping memory training upon subsequent reboots
… by using MRC cache.
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 73: its
that
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 81: with Intel.
Use two spaces for consistency instead of tab?
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 86: that
so
Done
Hello build bot (Jenkins), Patrick Rudolph, Ryback Hung, Paul Menzel, Angel Pons, Philipp Deppenwiese, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Morgan Jang, Bryant Ou, ron minnich, Ron Minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42947
to look at the new patch set (#3).
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e --- A Documentation/mainboard/ocp/deltalake.md 1 file changed, 109 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42947/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 3: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/42947/3/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/3/Documentation/mainboard/ocp... PS3, Line 11: one socket single-socket
https://review.coreboot.org/c/coreboot/+/42947/3/Documentation/mainboard/ocp... PS3, Line 11: Sacalable no a: Scalable
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 3:
(4 comments)
Thanks!
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 17: jointly develop FSP/coreboot/Linuxboot solution on Delta Lake as a hack project.
I'd like a better word than hack. In fact, I would remove "as a hack project" words entirely.
Done
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 93: CooperLake
Cooper Lake
Done
https://review.coreboot.org/c/coreboot/+/42947/3/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/3/Documentation/mainboard/ocp... PS3, Line 11: one socket
single-socket
Done
https://review.coreboot.org/c/coreboot/+/42947/3/Documentation/mainboard/ocp... PS3, Line 11: Sacalable
no a: Scalable
Done
Hello build bot (Jenkins), Patrick Rudolph, Ryback Hung, Paul Menzel, Angel Pons, Philipp Deppenwiese, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Morgan Jang, Bryant Ou, ron minnich, Ron Minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42947
to look at the new patch set (#4).
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e --- A Documentation/mainboard/ocp/deltalake.md 1 file changed, 111 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42947/4
Hello build bot (Jenkins), Patrick Rudolph, Ryback Hung, Paul Menzel, Angel Pons, Philipp Deppenwiese, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Morgan Jang, Bryant Ou, ron minnich, Ron Minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42947
to look at the new patch set (#5).
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e --- A Documentation/mainboard/ocp/deltalake.md 1 file changed, 128 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42947/5
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/2/Documentation/mainboard/ocp... PS2, Line 78: - VT-d is not supported. An IPS ticket is filed with Intel.
very good point. It would be nice to know more about this problem. […]
Though it could be fixed in a follow-up, so I’ll mark this as resolved, so this can be committed.
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/42947/1/Documentation/mainboard/ocp... PS1, Line 88: | BMC | Aspeed AST 2500 |
I am sorry, I am not sure I understand the comment and what needs to be changed.
I guess thats a joke here ;)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
Patch Set 5: Code-Review+2
Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42947 )
Change subject: doc/mb/ocp: Add documentation for Delta Lake ......................................................................
doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42947 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Christian Walter christian.walter@9elements.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- A Documentation/mainboard/ocp/deltalake.md 1 file changed, 128 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Christian Walter: Looks good to me, approved
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md new file mode 100644 index 0000000..c4c3284 --- /dev/null +++ b/Documentation/mainboard/ocp/deltalake.md @@ -0,0 +1,128 @@ +# OCP Delta Lake + +This page describes coreboot support status for the [OCP] (Open Compute Project) +Delta Lake server platform. + +## Introduction + +OCP Delta Lake server platform is a component of multi-host server system +Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020]. + +Delta Lake server is a single socket Cooper Lake Scalable Processor server. + +Yosemite-V3 has multiple configurations. Depending on configurations, it may +host up to 4 Delta Lake servers in one sled. + +Yosemite-V3 and Delta Lake are currently in DVT phase. Facebook, Intel and partners +jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative solution. + +## Required blobs + +This board currently requires: +- FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) + is not yet available to the public. It will be made public some time after the MP + (Mass Production) of CooperLake Scalable Processor when the FSP is mature. +- Microcode: Not yet available to the public. +- ME binary: Not yet available to the public. + +## Payload +- LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload. + U-root as initramfs, is used in the joint development. It can be built + following [All about u-root]. + +## Flashing coreboot + +To do in-band FW image update, use [flashrom]: + flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \ + -i bios --noverify-all -w <path to coreboot image> + +From OpenBMC, to update FW image: + fw-util slotx --update bios <path to coreboot image> + +To power off/on the host: + power-util slotx off + power-util slotx on + +To connect to console through SOL (Serial Over Lan): + sol-util slotx + +## Working features +The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root] +as initramfs. +- SMBIOS: + - Type 0 -- BIOS Information + - Type 1 -- System Information + - Type 2 -- Baseboard Information + - Type 3 -- System Enclosure or Chassis + - Type 4 -- Processor Information + - Type 8 -- Port Connector Information + - Type 9 -- PCI Slot Information + - Type 11 -- OEM String + - Type 13 -- BIOS Language Information + - Type 16 -- Physical Memory Array + - Type 19 -- Memory Array Mapped Address + - Type 127 -- End-of-Table + +- BMC integration: + - BMC readiness check + - IPMI commands + - watchdog timer + - POST complete pin acknowledgement +- SEL record generation +- Early serial output +- port 80h direct to GPIO +- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT +- Skipping memory training upon subsequent reboots by using MRC cache +- BMC crash dump +- Error injection through ITP + +## Firmware configurations +[ChromeOS VPD] is used to store most of the firmware configurations. +RO_VPD region holds default values, while RW_VPD region holds customized +values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses that value to populate smbios type 1 version field. + +## Known issues +- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not + support FSP_USES_CB_STACK. An IPS ticket is filed with Intel. +- VT-d is not supported. An IPS ticket is filed with Intel. +- PCIe bifuration is not supported. An IPS ticket is filed with Intel. +- ME based power capping. This is a bug in ME. An IPS ticket is filed + with Intel. +- RO_VPD region as well as other RO regions are not write protected. +- HECI is not set up correctly, so BMC is not able to get PCH and DIMM + temperature sensor readings. + +## Feature gaps +- Delta Lake DVT is not supported, as we only have Delta Lake EVT servers + at the moment. +- SMBIOS: + - Type 7 -- Cache Information + - Type 17 -- Memory Device + - Type 38 -- IPMI Device Information + - Type 41 -- Onboard Devices Extended Information +- ACPI: + - DMAR +- PFR/CBnT + +## Technology + +```eval_rst ++------------------------+---------------------------------------------+ +| Processor (1 socket) | Intel Cooper Lake Scalable Processor | ++------------------------+---------------------------------------------+ +| BMC | Aspeed AST 2500 | ++------------------------+---------------------------------------------+ +| PCH | Intel Lewisburg C621 | ++------------------------+---------------------------------------------+ +``` + +[OCP]: https://www.opencompute.org +[OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule +[flashrom]: https://flashrom.org/Flashrom +[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root +[u-root]: https://u-root.org/ +[ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
-
Angel Pons (Code Review) -
Christian Walter (Code Review)
-
Jonathan Zhang (Code Review)
-
Paul Menzel (Code Review)
-
Philipp Deppenwiese (Code Review)
-
ron minnich (Code Review)