Change in ...coreboot[master]: mb/google/sarien: Send post code to the EC

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32937

Change subject: mb/google/sarien: Send post code to the EC
......................................................................

mb/google/sarien: Send post code to the EC

Use the mainboard post code hook to inform the wilco EC driver of the
latest boot stage.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
TEST=Remove DIMM module, confirm diagnostic LED pattern for memory
failure (2 amber, 4 white).

Change-Id: If5bf69365d8be3bdbd433f305c85848206ded7b0
Signed-off-by: Duncan Laurie 
---
M src/mainboard/google/sarien/chromeos.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32937/1

diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c
index fafc469..622a9fa 100644
--- a/src/mainboard/google/sarien/chromeos.c
+++ b/src/mainboard/google/sarien/chromeos.c
@@ -21,6 +21,7 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <security/tpm/tss.h>
 #include <device/device.h>
+#include <ec/google/wilco/commands.h>
 #include <intelblocks/pmclib.h>
 #include <soc/pmc.h>
 #include <soc/pci_devs.h>
@@ -125,3 +126,8 @@
    pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_STATE_ON);
 #endif
 }
+
+void mainboard_post(uint8_t value)
+{
+	wilco_ec_save_post_code(value);
+}

[Duncan Laurie (Code Review)]

Hello Jett Rink,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32937

to look at the new patch set (#2).

Change subject: mb/google/sarien: Send post code to the EC
......................................................................

mb/google/sarien: Send post code to the EC

Use the mainboard post code hook to inform the wilco EC driver of the
latest boot stage.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
TEST=Remove DIMM module, confirm diagnostic LED pattern for memory
failure (2 amber, 4 white).

Change-Id: If5bf69365d8be3bdbd433f305c85848206ded7b0
Signed-off-by: Duncan Laurie 
---
M src/mainboard/google/sarien/ramstage.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32937/2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32937 )

Change subject: mb/google/sarien: Send post code to the EC
......................................................................

Patch Set 2: Code-Review+2

[Jett Rink (Code Review)]

Jett Rink has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32937 )

Change subject: mb/google/sarien: Send post code to the EC
......................................................................

Patch Set 3: Code-Review+1

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32937 )

Change subject: mb/google/sarien: Send post code to the EC
......................................................................

mb/google/sarien: Send post code to the EC

Use the mainboard post code hook to inform the wilco EC driver of the
latest boot stage.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
TEST=Remove DIMM module, confirm diagnostic LED pattern for memory
failure (2 amber, 4 white).

Change-Id: If5bf69365d8be3bdbd433f305c85848206ded7b0
Signed-off-by: Duncan Laurie 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32937
Reviewed-by: Jett Rink 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/sarien/ramstage.c
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Jett Rink: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index 1d22046..e246419 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -15,6 +15,7 @@

#include <arch/acpi.h>
 #include <drivers/vpd/vpd.h>
+#include <ec/google/wilco/commands.h>
 #include <smbios.h>
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
@@ -69,6 +70,11 @@
    cnl_configure_pads(gpio_table, num_gpios);
 }

+void mainboard_post(uint8_t value)
+{
+	wilco_ec_save_post_code(value);
+}
+
 static void mainboard_enable(struct device *dev)
 {
    dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;