Change in coreboot[master]: amd/stoneyridge: Create gnvs entries for AOAC devices

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28765

Change subject: amd/stoneyridge: Create gnvs entries for AOAC devices
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amd/stoneyridge: Create gnvs entries for AOAC devices

A later patch will leverage AMD's ASL support for handling AOAC
devices.  This will gather coreboot's device enables from a bitwise field,
where each bit corresponds to the register offset used to control
each devices.

Create an identical structure, and add it to the nvs ASL and global_nvs_t
structure.

BUG=b:77602074

Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/acpi/globalnvs.asl
M src/soc/amd/stoneyridge/include/soc/nvs.h
M src/soc/amd/stoneyridge/include/soc/southbridge.h
3 files changed, 42 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28765/1

diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
index ba50e38..f77d108 100644
--- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl
+++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
@@ -47,6 +47,24 @@
    TCRT,	8,	// 0x2E - Critical Threshold
    TPSV,	8,	// 0x2F - Passive Threshold
    TMAX,	8,	// 0x30 - CPU Tj_max
+	, 5,		// 0x31 - AOAC Device Enables
+	IC0E,	1,	//        I2C0, 5
+	IC1E,	1,	//        I2C1, 6
+	IC2E,	1,	//        I2C2, 7
+	IC3E,	1,	//        I2C3, 8
+	, 2,
+	UT0E,	1,	//        UART0, 11
+	UT1E,	1,	//        UART1, 12
+	, 2,
+	ST_E,	1,	//        SATA, 15
+	, 2,
+	EHCE,	1,	//        EHCI, 18
+	, 4,
+	XHCE,	1,	//        XCHI, 23
+	SD_E,	1,	//        SD, 24
+	, 2,
+	ESPI,	1,	//        ESPI, 27
+	, 4,
    /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
    Offset (0x100),
    #include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index bcac3a9..667f6ef 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -28,6 +28,7 @@
 #include <compiler.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/gnvs.h>
+#include <soc/southbridge.h>

typedef struct global_nvs_t {
    /* Miscellaneous */
@@ -50,7 +51,8 @@
    uint8_t		tcrt; /* 0x2E - Critical Threshold */
    uint8_t		tpsv; /* 0x2F - Passive Threshold */
    uint8_t		tmax; /* 0x30 - CPU Tj_max */
-	uint8_t		unused[207];
+	aoac_devs_t	aoac; /* 0x31 - AOAC device enables */
+	uint8_t		unused[203];

/* ChromeOS specific (0x100 - 0xfff) */
    chromeos_acpi_t chromeos;
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index f054b3b..3239842 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -400,6 +400,27 @@
    int status;
 };

+typedef struct aoac_devs {
+	int unused1:5;
+	int ic0e:1; /* 5: I2C0 */
+	int ic1e:1; /* 6: I2C1 */
+	int ic2e:1; /* 7: I2C2 */
+	int ic3e:1; /* 8: I2C3 */
+	int unused2:2;
+	int ut0e:1; /* 11: UART0 */
+	int ut1e:1; /* 12: UART0 */
+	int unused3:2;
+	int st_e:1; /* 15: SATA */
+	int unused4:2;
+	int ehce:1; /* 18: EHCI */
+	int unused5:4;
+	int xhce:1; /* 23: xHCI */
+	int sd_e:1; /* 24: SDIO */
+	int unused6:2;
+	int espi:1; /* 27: ESPI */
+	int unused7:4;
+} __packed aoac_devs_t;
+
 struct soc_power_reg {
    uint16_t pm1_sts;
    uint16_t pm1_en;