[XS] Change in coreboot[main]: mb/google/brox: Initialize TCHSCR_RST_L to 0

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80300?usp=email )

Change subject: mb/google/brox: Initialize TCHSCR_RST_L to 0
......................................................................

mb/google/brox: Initialize TCHSCR_RST_L to 0

TCHSCR_RST_L signal was originally being configured to 1 in gpio.c but
this was causing some leakage.  Configuring it to 0 initially should
fix this.

BUG=b:322249892
BRANCH=None
TEST=Make brox boots and touchscreen is still working

Change-Id: I5bf1901a3a40a38237b950abcb758f96aebcc1cf
Signed-off-by: Shelley Chen 
---
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/80300/1

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index 5432bd1..2f31ae8 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -262,7 +262,7 @@
    /* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# NF6: USB_C_GPP_F16] ==> PCH_TCHSCR_REPORT_EN */
    PAD_CFG_GPO(GPP_F16, 0, PLTRST),
    /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */
-	PAD_CFG_GPO(GPP_F17, 1, DEEP),
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
    /* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
    /* GPP_F19 : SRCCLKREQ6 ==> NC */