Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30927
to review the following change.
Change subject: drivers/spi/sst.c: Add three remaining SST25*F080 chips ......................................................................
drivers/spi/sst.c: Add three remaining SST25*F080 chips
Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: Idc63665937ab1bfdf15c4054001daa288bfdd47b --- M src/drivers/spi/sst.c 1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30927/1
diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 559969a..63fae95 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -78,6 +78,11 @@ .name = "SST25VF080B", .ops = &spi_flash_ops_write_ai, },{ + .idcode1 = 0x80, + .nr_sectors = 256, + .name = "SST25VF080", + .ops = &spi_flash_ops_write_ai, + },{ .idcode1 = 0x41, .nr_sectors = 512, .name = "SST25VF016B", @@ -112,6 +117,16 @@ .nr_sectors = 128, .name = "SST25WF040", .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x05, + .nr_sectors = 256, + .name = "SST25WF080", + .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x14, + .nr_sectors = 256, + .name = "SST25WF080B", + .ops = &spi_flash_ops_write_ai, }, };
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30927 )
Change subject: drivers/spi/sst.c: Add three remaining SST25*F080 chips ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/#/c/30927/1/src/drivers/spi/sst.c File src/drivers/spi/sst.c:
https://review.coreboot.org/#/c/30927/1/src/drivers/spi/sst.c@80 PS1, Line 80: },{ space required after that ',' (ctx:VxV)
https://review.coreboot.org/#/c/30927/1/src/drivers/spi/sst.c@120 PS1, Line 120: },{ space required after that ',' (ctx:VxV)
https://review.coreboot.org/#/c/30927/1/src/drivers/spi/sst.c@125 PS1, Line 125: },{ space required after that ',' (ctx:VxV)
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30927 )
Change subject: drivers/spi/sst.c: Add three remaining SST25*F080 chips ......................................................................
Patch Set 1: Code-Review+2
Stefan Reinauer has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30927 )
Change subject: drivers/spi/sst.c: Add three remaining SST25*F080 chips ......................................................................
drivers/spi/sst.c: Add three remaining SST25*F080 chips
Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: Idc63665937ab1bfdf15c4054001daa288bfdd47b Reviewed-on: https://review.coreboot.org/c/30927 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/spi/sst.c 1 file changed, 15 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 559969a..63fae95 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -78,6 +78,11 @@ .name = "SST25VF080B", .ops = &spi_flash_ops_write_ai, },{ + .idcode1 = 0x80, + .nr_sectors = 256, + .name = "SST25VF080", + .ops = &spi_flash_ops_write_ai, + },{ .idcode1 = 0x41, .nr_sectors = 512, .name = "SST25VF016B", @@ -112,6 +117,16 @@ .nr_sectors = 128, .name = "SST25WF040", .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x05, + .nr_sectors = 256, + .name = "SST25WF080", + .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x14, + .nr_sectors = 256, + .name = "SST25WF080B", + .ops = &spi_flash_ops_write_ai, }, };
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build bot (Jenkins) (Code Review) -
Kyösti Mälkki (Code Review)
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mikeb mikeb (Code Review)
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Stefan Reinauer (Code Review)