Change in coreboot[master]: soc/intel/*: Update microcode as specified for MP-init

[Michael Niewöhner (Code Review)]

Attention is currently required from: Nico Huber, Patrick Rudolph, Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Nathaniel L Desimone.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49899 )

Change subject: soc/intel/*: Update microcode as specified for MP-init
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Patch Set 13:

(1 comment)

File src/soc/intel/alderlake/cpu.c:

https://review.coreboot.org/c/coreboot/+/49899/comment/fc36d69c_be8f401f 
PS13, Line 70: PRMRR
> PRMRR isn't currently configured on those platforms, so a second microcode update isn't required at all?

Well, "not configured" would look different ;)

src/soc/intel/tigerlake/romstage/fsp_params.c:	m_cfg->PrmrrSize = get_valid_prmrr_size();
src/soc/intel/icelake/romstage/fsp_params.c:	m_cfg->PrmrrSize = get_valid_prmrr_size();
src/soc/intel/alderlake/romstage/fsp_params.c:	m_cfg->PrmrrSize = get_valid_prmrr_size();

However, they don't select SOC_INTEL_COMMON_BLOCK_SGX, so PrmrrSize will be zero. When any board sets enable_c6dram=1, Fsp set PrmrrSize=1MB.

CpuMpPpi is used (SkipMpInit=0), FSP handles the microcode reload at "End of PEI", so coreboot doesn't have to do that.

When we want to revive SkipMpInit=1, we'll need to do the reload.