Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47207 )
Change subject: sb/intel: Don't set ACPI_EN twice ......................................................................
sb/intel: Don't set ACPI_EN twice
It is already done once when enabling PMBASE in early init.
Change-Id: I14289c9164ee1488c192fce721d86c89fa5cc736 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 7 files changed, 3 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47207/1
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 452adb1..767d3ad 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -222,7 +222,7 @@
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index df5625a..2c3b10a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -44,9 +44,6 @@ pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
- /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index eb59eb0..ea73322 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -35,9 +35,6 @@ */ static void i82801gx_enable_ioapic(struct device *dev) { - /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index ace09e2..df380c5 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -33,7 +33,7 @@
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
printk(BIOS_DEBUG, " done.\n");
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 8269dd9..4f622dd 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -39,9 +39,6 @@ { u32 reg32;
- /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x01); /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 465aa1e..8cc6a87 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -40,7 +40,7 @@
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4286e6ca..b56ace8 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -41,9 +41,6 @@ pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
- /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47207 )
Change subject: sb/intel: Don't set ACPI_EN twice ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/47207/3/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/lpc.c:
https://review.coreboot.org/c/coreboot/+/47207/3/src/southbridge/intel/bd82x... PS3, Line 48: pci_write_config8(dev, ACPI_CNTL, ACPI_EN); Did somebody shuffle the letters of APIC here? xD
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47207 )
Change subject: sb/intel: Don't set ACPI_EN twice ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47207/3/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/lpc.c:
https://review.coreboot.org/c/coreboot/+/47207/3/src/southbridge/intel/bd82x... PS3, Line 48: pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
Did somebody shuffle the letters of APIC here? xD
I guess 😄
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47207 )
Change subject: sb/intel: Don't set ACPI_EN twice ......................................................................
sb/intel: Don't set ACPI_EN twice
It is already done once when enabling PMBASE in early init.
Change-Id: I14289c9164ee1488c192fce721d86c89fa5cc736 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47207 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 7 files changed, 3 insertions(+), 15 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 452adb1..767d3ad 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -222,7 +222,7 @@
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index a498f87..8af8065 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -44,9 +44,6 @@ pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
- /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 721735c..9ac8942 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -35,9 +35,6 @@ */ static void i82801gx_enable_ioapic(struct device *dev) { - /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index ace09e2..df380c5 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -33,7 +33,7 @@
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
printk(BIOS_DEBUG, " done.\n");
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index dddecd7..d2a3404 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -39,9 +39,6 @@ { u32 reg32;
- /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x01); /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 465aa1e..8cc6a87 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -40,7 +40,7 @@
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 2872a0b..2db4b59 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -41,9 +41,6 @@ pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
- /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
-
Angel Pons (Code Review) -
Nico Huber (Code Review)