Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32318
Change subject: nb/intel/nehalem: Hide some raminit output messages ......................................................................
nb/intel/nehalem: Hide some raminit output messages
Hide some debug output behind CONFIG_DEBUG_RAM_SETUP. That way the pre-ram console does not overflow.
Change-Id: Idc425f4d10443f6ee7f9b4da67eb6542069cc40c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/raminit.c 2 files changed, 19 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/32318/1
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 9eb6e75..1e50459 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -23,6 +23,7 @@ select CACHE_MRC_SETTINGS select POSTCAR_STAGE select POSTCAR_CONSOLE + select HAVE_DEBUG_RAM_SETUP
if NORTHBRIDGE_INTEL_NEHALEM
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 78bc6de..3164a58 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1568,14 +1568,14 @@ static void dump_timings(struct raminfo *info) { int channel, slot, rank, lane, i; - printk(BIOS_DEBUG, "Timings:\n"); + printk(RAM_DEBUG, "Timings:\n"); FOR_POPULATED_RANKS { - printk(BIOS_DEBUG, "channel %d, slot %d, rank %d\n", channel, + printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel, slot, rank); for (lane = 0; lane < 9; lane++) { - printk(BIOS_DEBUG, "lane %d: ", lane); + printk(RAM_DEBUG, "lane %d: ", lane); for (i = 0; i < 4; i++) { - printk(BIOS_DEBUG, "%x (%x) ", + printk(RAM_DEBUG, "%x (%x) ", read_500(info, channel, get_timing_register_addr (lane, i, slot, rank), @@ -1584,12 +1584,12 @@ lane_timings[i][channel][slot][rank] [lane]); } - printk(BIOS_DEBUG, "\n"); + printk(RAM_DEBUG, "\n"); } } - printk(BIOS_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), + printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), info->training.reg_178); - printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), + printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), info->training.reg_10b); }
@@ -1623,8 +1623,8 @@ train.reg_6dc = MCHBAR32(0x6dc); train.reg_6e8 = MCHBAR32(0x6e8);
- printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc); - printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); + printk(RAM_SPEW, "[6dc] = %x\n", train.reg_6dc); + printk(RAM_SPEW, "[6e8] = %x\n", train.reg_6e8);
/* Save the MRC S3 restore data to cbmem */ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, @@ -3403,7 +3403,7 @@ 0, 1, &ratios2); compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1, &ratios1); - printk (BIOS_SPEW, "[%x] <= %x\n", reg, + printk(RAM_SPEW, "[%x] <= %x\n", reg, ratios1.freq4_to_max_remainder | (ratios2. freq4_to_max_remainder << 8) @@ -3486,7 +3486,8 @@ frequency_11(info) / 2, 4000, 4000, 0, 0);
if (s3resume) { - printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc); + printk(RAM_SPEW, "[6dc] <= %x\n", + info->cached_training->reg_6dc); MCHBAR32(0x6dc) = info->cached_training->reg_6dc; } else set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, @@ -3497,7 +3498,8 @@ set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, frequency_11(info) / 2, 3500, 0, 0, 0); if (s3resume) { - printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8); + printk(RAM_SPEW, "[6e8] <= %x\n", + info->cached_training->reg_6e8); MCHBAR32(0x6e8) = info->cached_training->reg_6e8; } else set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, @@ -4026,19 +4028,19 @@ int j; if (s3resume && info.cached_training) { restore_274265(&info); - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", info.cached_training->reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", i, j, info.cached_training->reg274265[i][j]); } else { set_274265(&info); - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", info.training.reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", i, j, info.training.reg274265[i][j]); }
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32318 )
Change subject: nb/intel/nehalem: Hide some raminit output messages ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/32318/1/src/northbridge/intel/nehalem/ramini... File src/northbridge/intel/nehalem/raminit.c:
https://review.coreboot.org/#/c/32318/1/src/northbridge/intel/nehalem/ramini... PS1, Line 1569: { Could also bail out early `if (!CONFIG(DEBUG_RAM_SETUP))`. But maybe that would require more extensive testing? who knows what removing this code can cause ;)
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32318 )
Change subject: nb/intel/nehalem: Hide some raminit output messages ......................................................................
nb/intel/nehalem: Hide some raminit output messages
Hide some debug output behind CONFIG_DEBUG_RAM_SETUP. That way the pre-ram console does not overflow.
Change-Id: Idc425f4d10443f6ee7f9b4da67eb6542069cc40c Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/32318 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/raminit.c 2 files changed, 19 insertions(+), 16 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 9eb6e75..1e50459 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -23,6 +23,7 @@ select CACHE_MRC_SETTINGS select POSTCAR_STAGE select POSTCAR_CONSOLE + select HAVE_DEBUG_RAM_SETUP
if NORTHBRIDGE_INTEL_NEHALEM
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 78bc6de..3164a58 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1568,14 +1568,14 @@ static void dump_timings(struct raminfo *info) { int channel, slot, rank, lane, i; - printk(BIOS_DEBUG, "Timings:\n"); + printk(RAM_DEBUG, "Timings:\n"); FOR_POPULATED_RANKS { - printk(BIOS_DEBUG, "channel %d, slot %d, rank %d\n", channel, + printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel, slot, rank); for (lane = 0; lane < 9; lane++) { - printk(BIOS_DEBUG, "lane %d: ", lane); + printk(RAM_DEBUG, "lane %d: ", lane); for (i = 0; i < 4; i++) { - printk(BIOS_DEBUG, "%x (%x) ", + printk(RAM_DEBUG, "%x (%x) ", read_500(info, channel, get_timing_register_addr (lane, i, slot, rank), @@ -1584,12 +1584,12 @@ lane_timings[i][channel][slot][rank] [lane]); } - printk(BIOS_DEBUG, "\n"); + printk(RAM_DEBUG, "\n"); } } - printk(BIOS_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), + printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), info->training.reg_178); - printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), + printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), info->training.reg_10b); }
@@ -1623,8 +1623,8 @@ train.reg_6dc = MCHBAR32(0x6dc); train.reg_6e8 = MCHBAR32(0x6e8);
- printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc); - printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); + printk(RAM_SPEW, "[6dc] = %x\n", train.reg_6dc); + printk(RAM_SPEW, "[6e8] = %x\n", train.reg_6e8);
/* Save the MRC S3 restore data to cbmem */ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, @@ -3403,7 +3403,7 @@ 0, 1, &ratios2); compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1, &ratios1); - printk (BIOS_SPEW, "[%x] <= %x\n", reg, + printk(RAM_SPEW, "[%x] <= %x\n", reg, ratios1.freq4_to_max_remainder | (ratios2. freq4_to_max_remainder << 8) @@ -3486,7 +3486,8 @@ frequency_11(info) / 2, 4000, 4000, 0, 0);
if (s3resume) { - printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc); + printk(RAM_SPEW, "[6dc] <= %x\n", + info->cached_training->reg_6dc); MCHBAR32(0x6dc) = info->cached_training->reg_6dc; } else set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, @@ -3497,7 +3498,8 @@ set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, frequency_11(info) / 2, 3500, 0, 0, 0); if (s3resume) { - printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8); + printk(RAM_SPEW, "[6e8] <= %x\n", + info->cached_training->reg_6e8); MCHBAR32(0x6e8) = info->cached_training->reg_6e8; } else set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, @@ -4026,19 +4028,19 @@ int j; if (s3resume && info.cached_training) { restore_274265(&info); - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", info.cached_training->reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", i, j, info.cached_training->reg274265[i][j]); } else { set_274265(&info); - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", info.training.reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", i, j, info.training.reg274265[i][j]); }
-
Arthur Heymans (Code Review) -
Martin Roth (Code Review)
-
Nico Huber (Code Review)