Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62973 )

Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
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mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s

GL9763e doesn’t support L0s state, so disable L0s at the root port.

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Kevin Chang 
Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
Reviewed-by: Peichao Wang 
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Peichao Wang: Looks good to me, approved
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 75672ae..b4cda82 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -407,6 +407,7 @@
    			.clk_src = 0,
    			.clk_req = 0,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L1,
    		}"
    		chip soc/intel/common/block/pcie/rtd3
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"