Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39367 )
Change subject: src/soc/tigerlake: add S0ix support fsp_params
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39367/3/src/soc/intel/tigerlake/fsp...
File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39367/3/src/soc/intel/tigerlake/fsp...
PS3, Line 162: params->PmcLpmS0ixSubStateEnableMask = 0x09;
: params->PchFivrVccinAuxLowToHighCurModeVolTranTime = 0;
: params->PchFivrVccinAuxRetToHighCurModeVolTranTime = 0;
: params->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0;
I would like to understand from Intel what these mean and why these are required?
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Gerrit-Project: coreboot
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