HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31005
Change subject: i945,ICH7: Add 'FIXME' comment on R/WO register ......................................................................
i945,ICH7: Add 'FIXME' comment on R/WO register
RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c Drop one of them.
Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/early_init.c M src/southbridge/intel/i82801gx/pcie.c 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31005/1
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 528f1aa..09a18e3 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -347,6 +347,7 @@ RCBA32(V0CTL) = 0x80000001; RCBA32(V1CAP) = 0x03128010;
+ /* FIXME: RPFN R/WO register and i82801gx/pcie.c try to rewrite */ RCBA32(RPFN) = 0x00543210;
pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index c0f9c12..9d218c7 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -25,6 +25,7 @@
struct root_port_config { /* RPFN is a write-once register so keep a copy until it is written */ + /* FIXME: already written here intel/i945/early_init.c */ u32 orig_rpfn; u32 new_rpfn; int num_ports;
Hello Kyösti Mälkki, Patrick Rudolph, Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31005
to look at the new patch set (#2).
Change subject: i945,ICH7: Write on RPFN only once ......................................................................
i945,ICH7: Write on RPFN only once
RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c Drop the romstage write.
Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/early_init.c 1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31005/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31005 )
Change subject: i945,ICH7: Write on RPFN only once ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31005 )
Change subject: i945,ICH7: Write on RPFN only once ......................................................................
Patch Set 2: Code-Review+1
(4 comments)
https://review.coreboot.org/#/c/31005/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31005/2//COMMIT_MSG@7 PS2, Line 7: Write on Just *Write* without *on*.
https://review.coreboot.org/#/c/31005/2//COMMIT_MSG@7 PS2, Line 7: i945,ICH7 Maybe:
intel/i945,ich7: …
https://review.coreboot.org/#/c/31005/2//COMMIT_MSG@10 PS2, Line 10: Drop the romstage write. Do both write the same value? Why drop the romstage one?
From `src/southbridge/intel/i82801gx/pcie.c`:
RCBA32(RPFN) = rpc.new_rpfn;
https://review.coreboot.org/#/c/31005/2//COMMIT_MSG@11 PS2, Line 11: Tested how?
Hello Kyösti Mälkki, Patrick Rudolph, Arthur Heymans, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31005
to look at the new patch set (#3).
Change subject: i945,ICH7: Add 'FIXME' comment on R/WO register ......................................................................
i945,ICH7: Add 'FIXME' comment on R/WO register
RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c Drop one of them.
Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/early_init.c M src/southbridge/intel/i82801gx/pcie.c 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31005/3
Hello Kyösti Mälkki, Patrick Rudolph, Arthur Heymans, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31005
to look at the new patch set (#4).
Change subject: i945,ICH7: Write on RPFN only once ......................................................................
i945,ICH7: Write on RPFN only once
RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c Drop the romstage write.
Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/early_init.c 1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31005/4
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31005 )
Change subject: i945,ICH7: Write on RPFN only once ......................................................................
i945,ICH7: Write on RPFN only once
RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c Drop the romstage write.
Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/31005 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/northbridge/intel/i945/early_init.c 1 file changed, 0 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 6bfa1c7..be882de 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -354,8 +354,6 @@ RCBA32(HDD) = 0x0f000003; RCBA32(RP5D) = 0x05000002;
- RCBA32(RPFN) = 0x00543210; - pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141);