Attention is currently required from: Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Balaji Manigandan, Aamir Bohra. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49731 )
Change subject: mb/intel/shadowmountain: Add the romstage code ......................................................................
Patch Set 2:
(3 comments)
File src/mainboard/intel/shadowmountain/spd/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/49731/comment/5a4e95b2_d9b22d4f PS1, Line 4: SPD_SOURCES += empty # 0b001
u don't need empty SPD, please remove
Done
File src/mainboard/intel/shadowmountain/spd/empty.spd.hex:
PS1:
There should be an empty SPD somewhere else.
Removed it.
File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49731/comment/d495b82c_bf103c26 PS1, Line 22: # Enable PCH PCIE RP 5 using CLK 1 : register "PchPcieRpEnable[4]" = "1" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcUsage[1]" = "0x4" : register "PcieRpClkReqDetect[4]" = "1" : : # Enable NVMe PCIE 9 using clk 0 : register "PchPcieRpEnable[8]" = "1" : register "PcieRpLtrEnable[8]" = "1" : register "PcieClkSrcUsage[0]" = "8" : register "PcieClkSrcClkReq[0]" = "0" : : # Enable SD Card PCIE 8 using clk 3 : register "PchPcieRpEnable[7]" = "1" : register "PcieRpLtrEnable[7]" = "1" : register "PcieRpHotPlug[7]" = "1" : register "PcieClkSrcUsage[3]" = "7" : register "PcieClkSrcClkReq[3]" = "3"
Note: This will need to be adapted once CB:48340 lands
Yes, i will push a separate CL for this.
-
V Sowmya (Code Review)