Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46142 )
Change subject: Signed-off-by: Johnny Li johnny_li@wistron.corp-partner.google.com Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f ......................................................................
Signed-off-by: Johnny Li johnny_li@wistron.corp-partner.google.com Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46142/1
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 0bb82f1..f0cf02d 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -4,6 +4,49 @@ register "IomTypeCPortPadCfg[1]" = "0x090E000D" register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }"
device domain 0 on device pci 05.0 on end # IPU 0x9A19
Johnny Li has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/46142 )
Change subject: mb/google/volteer/var/volteer: I2C5 trackpad bus freq 400 kHz ......................................................................
mb/google/volteer/var/volteer: I2C5 trackpad bus freq 400 kHz
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz.
BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li johnny_li@wistron.corp-partner.google.com Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46142/2
Johnny Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46142 )
Change subject: mb/google/volteer/var/volteer: I2C5 trackpad bus freq 400 kHz ......................................................................
Patch Set 2:
build bot fail can someone help
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46142 )
Change subject: mb/google/volteer/var/volteer: I2C5 trackpad bus freq 400 kHz ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46142/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46142/2//COMMIT_MSG@7 PS2, Line 7: volteer volteer2
Hello build bot (Jenkins), Caveh Jalali, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46142
to look at the new patch set (#3).
Change subject: mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz ......................................................................
mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz.
BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li johnny_li@wistron.corp-partner.google.com Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46142/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46142 )
Change subject: mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46142/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer2/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46142/3/src/mainboard/google/voltee... PS3, Line 23: .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, I'm not sure we have verified this yet in TGL?
https://review.coreboot.org/c/coreboot/+/46142/3/src/mainboard/google/voltee... PS3, Line 24: .gspi[0] = { : .speed_mhz = 1, : .early_init = 1, : }, This should go in the baseboard, they all have cr50 on gspi0
Hello build bot (Jenkins), Caveh Jalali, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46142
to look at the new patch set (#4).
Change subject: mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz ......................................................................
mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz.
BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li johnny_li@wistron.corp-partner.google.com Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46142/4
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46142 )
Change subject: mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz ......................................................................
Patch Set 4: Code-Review+2
Johnny Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46142 )
Change subject: mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz ......................................................................
Patch Set 4:
(2 comments)
Done
https://review.coreboot.org/c/coreboot/+/46142/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46142/2//COMMIT_MSG@7 PS2, Line 7: volteer
volteer2
google/volteer/variants/volteer2
https://review.coreboot.org/c/coreboot/+/46142/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer2/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46142/3/src/mainboard/google/voltee... PS3, Line 24: .gspi[0] = { : .speed_mhz = 1, : .early_init = 1, : },
This should go in the baseboard, they all have cr50 on gspi0
ok i will remove it
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46142 )
Change subject: mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46142/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46142/2//COMMIT_MSG@7 PS2, Line 7: volteer
google/volteer/variants/volteer2
Done
https://review.coreboot.org/c/coreboot/+/46142/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer2/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46142/3/src/mainboard/google/voltee... PS3, Line 23: .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
I'm not sure we have verified this yet in TGL?
Done
https://review.coreboot.org/c/coreboot/+/46142/3/src/mainboard/google/voltee... PS3, Line 24: .gspi[0] = { : .speed_mhz = 1, : .early_init = 1, : },
ok i will remove it
Done
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46142 )
Change subject: mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz ......................................................................
mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz.
BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li johnny_li@wistron.corp-partner.google.com Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f Reviewed-on: https://review.coreboot.org/c/coreboot/+/46142 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 38 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 2db1f08..3f666ac 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -4,6 +4,44 @@ register "IomTypeCPortPadCfg[1]" = "0x090E000D" register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }"
register "HybridStorageMode" = "1"