Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded

[Arthur Heymans (Code Review)]

Attention is currently required from: Arthur Heymans, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Werner Zeh, Angel Pons, Patrick Rudolph.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )

Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
......................................................................

Patch Set 2:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62566/comment/e4200b7d_726f0fb9 
PS2, Line 15: Now, in this scenario, the SPI
            : flash linear address range is not registered as a resource (since the
            : common SPI driver in src/soc/intel/common/block/spi is shared across
            : multiple SPI controllers and therefore cannot distinguish where the
            : flash is actually located at)
I don't understand this. It's in common so that means it knows about the memory mapped flash for all platforms? That is what the code in block/fast_spi seems to do.

There really should be something reserving that resource range as the allocator will otherwise use to to put PCI bars there.

https://review.coreboot.org/c/coreboot/+/62566/comment/f8d60506_885e4f34 
PS2, Line 20: The result of this chain is
            : that loading the payload from flash takes much longer now (on mc_ehl1 it
            : takes ~12 seconds for 4.5 MB).
Interesting. I checked this on OCP/Deltalake not long ago and the time loading the payload (kernel) was unaffected. For some platforms loading from UC flash to WB is actually faster than WP to WB, so maybe an extra Kconfig flag is desirable here?