Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Kane Chen.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )

Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
......................................................................

Patch Set 5:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/63293/comment/2f378d56_7507f086 
PS3, Line 11: informatrion
> information

Ack

Patchset:

PS2:
> Can we at least add the Problem statement from the TA?

Sure, I will add in other CL where .

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63293/comment/41225d5e_4fad9972 
PS4, Line 571: Enable
> I'd use `Disable` instead, given the option's name

Ack

https://review.coreboot.org/c/coreboot/+/63293/comment/06f59cc7_d4f5e5c7 
PS4, Line 572: Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating.
> I feel this is redundant. […]

I will add the comment in other CL.