Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44710
to review the following change.
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 84 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/1
diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index b5b262b..091b21b 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3791,6 +3791,7 @@ dramc_setting(cali); dramc_reset_delay_chain_before_calibration(); dramc_8_phase_cal(cali); + dramc_duty_calibration(cali->params); }
static void dramc_before_calibration(const struct ddr_cali *cali) diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 22a2545..e1f3d67 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -579,3 +579,86 @@ for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); } + +static void duty_delay_reg_convert(s8 duty_delay, u8 *delay) +{ + u8 delay_tmp; + + if (duty_delay < 0) + delay_tmp = -duty_delay; + else if (duty_delay > 0) + delay_tmp = duty_delay + (1 << 5); + else + delay_tmp = 0; + + *delay = delay_tmp; +} + +static void dramc_duty_set_clk_delay_cell(u8 chn, const s8* duty_delay) +{ + u8 delay_tmp; + + duty_delay_reg_convert(duty_delay[0], &delay_tmp); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_txduty, + SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY, delay_tmp); +} + +static void dramc_duty_set_dqs_delay_cell(u8 chn, const s8* duty_delay) +{ + u8 dqs; + u8 delay_tmp[DQS_NUMBER]; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &(delay_tmp[dqs])); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0, delay_tmp[dqs]); + } +} + + +static void dramc_duty_set_wck_delay_cell(u8 chn, const s8* duty_delay) +{ + u8 dqs; + u8 delay_tmp[DQS_NUMBER]; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &(delay_tmp[dqs])); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0, delay_tmp[dqs]); + } +} + +static void dramc_duty_set_dqdqm_delay_cell(u8 chn, + const s8* duty_delay, u8 k_type) +{ + u8 dqs; + u8 delay_tmp[DQS_NUMBER]; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &(delay_tmp[dqs])); + + if (k_type == DutyScan_K_DQ) + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0, delay_tmp[dqs]); + else if (k_type == DutyScan_K_DQM) + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0, delay_tmp[dqs]); + } +} + +void dramc_duty_calibration(const struct sdram_params *params) +{ + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay_cell(chn, params->duty_clk_delay[chn]); + dramc_duty_set_dqs_delay_cell(chn, params->duty_dqs_delay[chn]); + dramc_duty_set_wck_delay_cell(chn, params->duty_wck_delay[chn]); + dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dqm_delay[chn], + DutyScan_K_DQM); + dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dq_delay[chn], + DutyScan_K_DQ); + } + + dramc_set_broadcast(bc_bak); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44710/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44710/1/src/soc/mediatek/mt8192/dra... PS1, Line 597: static void dramc_duty_set_clk_delay_cell(u8 chn, const s8* duty_delay) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44710/1/src/soc/mediatek/mt8192/dra... PS1, Line 606: static void dramc_duty_set_dqs_delay_cell(u8 chn, const s8* duty_delay) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44710/1/src/soc/mediatek/mt8192/dra... PS1, Line 619: static void dramc_duty_set_wck_delay_cell(u8 chn, const s8* duty_delay) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44710/1/src/soc/mediatek/mt8192/dra... PS1, Line 632: const s8* duty_delay, u8 k_type) "foo* bar" should be "foo *bar"
Hello build bot (Jenkins), Julius Werner, Duan huayang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44710
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/2
Yidi Lin has uploaded a new patch set (#24) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/24
Yidi Lin has uploaded a new patch set (#34) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/34
Yidi Lin has uploaded a new patch set (#36) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/36
Xi Chen has uploaded a new patch set (#37) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/37
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
Patch Set 40: Code-Review+2
Yidi Lin has uploaded a new patch set (#43) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/43
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
Patch Set 44:
(11 comments)
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 573: delay_tmp We could directly assign values to *delay.
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 587: delay_tmp Just "delay"
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 589: duty_delay_reg_convert Don't we need to do the same for duty_delay[1] (because RANK_MAX is 2)?
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 597: delay_tmp No need to use an array.
u8 delay.
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 599: DQS_NUMBER Should we use DQS_NUMBER_LP4 to match the declaration in dramc_param.h? I know they're the same.
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 600: ( No need for parentheses.
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 609: delay_tmp Same
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 612: ( Same
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 618: static void dramc_duty_set_dqdqm_delay_cell(u8 chn, : const s8 *duty_delay, u8 k_type) Write
static void dramc_duty_set_dqdqm_delay_cell(u8 chn, const s8 *duty_delay, u8 k_type)
or
static void dramc_duty_set_dqdqm_delay_cell( u8 chn, const s8 *duty_delay, u8 k_type)
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 622: delay_tmp Same
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 625: ( Same
Xi Chen has uploaded a new patch set (#46) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/46
Xi Chen has uploaded a new patch set (#48) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/48
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
Patch Set 48:
(11 comments)
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 573: delay_tmp
We could directly assign values to *delay.
Ack
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 587: delay_tmp
Just "delay"
Ack
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 589: duty_delay_reg_convert
Don't we need to do the same for duty_delay[1] (because RANK_MAX is 2)?
RANK0 and RANK1 share the same duty delay, use RANK0 is ok.
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 597: delay_tmp
No need to use an array. […]
Ack
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 599: DQS_NUMBER
Should we use DQS_NUMBER_LP4 to match the declaration in dramc_param.h? I know they're the same.
DQS_NUMBER is for common, dram_param DQS_NUMBER_LP4 is for LP4, keep DQS_NUMBER here.
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 600: (
No need for parentheses.
Ack
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 609: delay_tmp
Same
Ack
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 612: (
Same
Ack
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 618: static void dramc_duty_set_dqdqm_delay_cell(u8 chn, : const s8 *duty_delay, u8 k_type)
Write […]
Ack
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 622: delay_tmp
Same
Ack
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 625: (
Same
Ack
Xi Chen has uploaded a new patch set (#49) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/49
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
Patch Set 49:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 589: duty_delay_reg_convert
RANK0 and RANK1 share the same duty delay, use RANK0 is ok.
Ack
https://review.coreboot.org/c/coreboot/+/44710/44/src/soc/mediatek/mt8192/dr... PS44, Line 599: DQS_NUMBER
DQS_NUMBER is for common, dram_param DQS_NUMBER_LP4 is for LP4, keep DQS_NUMBER here.
Ack
https://review.coreboot.org/c/coreboot/+/44710/49/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44710/49/src/soc/mediatek/mt8192/dr... PS49, Line 595: 0 RANK_0
Xi Chen has uploaded a new patch set (#50) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/50
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
Patch Set 50:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44710/49/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44710/49/src/soc/mediatek/mt8192/dr... PS49, Line 595: 0
RANK_0
Ack
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
Patch Set 50: Code-Review+2
Xi Chen has uploaded a new patch set (#53) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44710/53
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44710 )
Change subject: soc/mediatek/mt8192: Do dramc duty calibration ......................................................................
soc/mediatek/mt8192: Do dramc duty calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44710 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 79 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 24f9620..eeeecea 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3791,6 +3791,7 @@ dramc_setting(cali); dramc_reset_delay_chain_before_calibration(); dramc_8_phase_cal(cali); + dramc_duty_calibration(cali->params); }
static void dramc_before_calibration(const struct ddr_cali *cali) diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 19a964a..e4dc896 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -577,3 +577,81 @@ for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); } + +static void duty_delay_reg_convert(s8 duty_delay, u8 *delay) +{ + if (duty_delay < 0) + *delay = -duty_delay; + else if (duty_delay > 0) + *delay = duty_delay + (1 << 5); + else + *delay = 0; +} + +static void dramc_duty_set_clk_delay_cell(u8 chn, const s8 *duty_delay) +{ + u8 delay; + + duty_delay_reg_convert(duty_delay[RANK_0], &delay); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_txduty, + SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY, delay); +} + +static void dramc_duty_set_dqs_delay_cell(u8 chn, const s8 *duty_delay) +{ + u8 dqs; + u8 delay; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &delay); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0, delay); + } +} + +static void dramc_duty_set_wck_delay_cell(u8 chn, const s8 *duty_delay) +{ + u8 dqs; + u8 delay; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &delay); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0, delay); + } +} + +static void dramc_duty_set_dqdqm_delay_cell(u8 chn, const s8 *duty_delay, + u8 k_type) +{ + u8 dqs; + u8 delay; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &delay); + + if (k_type == DUTYSCAN_K_DQ) + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0, delay); + else if (k_type == DUTYSCAN_K_DQM) + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0, delay); + } +} + +void dramc_duty_calibration(const struct sdram_params *params) +{ + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay_cell(chn, params->duty_clk_delay[chn]); + dramc_duty_set_dqs_delay_cell(chn, params->duty_dqs_delay[chn]); + dramc_duty_set_wck_delay_cell(chn, params->duty_wck_delay[chn]); + dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dqm_delay[chn], + DUTYSCAN_K_DQM); + dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dq_delay[chn], + DUTYSCAN_K_DQ); + } + + dramc_set_broadcast(bc_bak); +}
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build bot (Jenkins) (Code Review) -
CK HU (Code Review)
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Hung-Te Lin (Code Review)
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Xi Chen (Code Review)
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Yidi Lin (Code Review)
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Yu-Ping Wu (Code Review)