Change in coreboot[master]: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE - coreboot-gerrit

21 Apr 2022


      Attention is currently required from: Arthur Heymans, Nico Huber, Angel Pons, Alexander Couzens, Patrick Rudolph, Swift Geek (Sebastian Grzywna).
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52942 )
Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
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Patch Set 1:
(1 comment)
File src/cpu/intel/socket_p/Kconfig:
https://review.coreboot.org/c/coreboot/+/52942/comment/2274f00a_1f710095 
PS1, Line 16: 	default 0x10000
...
I had swiftgeek test CB:54002 on X200
Done
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Gerrit-Change-Number: 52942
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: Alexander Couzens lynxis@fe80.eu
Gerrit-Reviewer: Nico Huber nico.h@gmx.de
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