Change in coreboot[master]: soc/intel/common/gspi: Check device validity before setting state

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Check device validity before setting state
......................................................................

soc/intel/common/gspi: Check device validity before setting state

Not all GSPI devices are enabled in all SoCs. Ensure that the GSPI
device is valid before setting controller state to active.

BUG=None
TEST=Boot to ChromeOS.

Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34761/1

diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index beb12fb..4a5b3b9 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -479,7 +479,8 @@
    }

/* Ensure controller is in D0 state */
-	lpss_set_power_state(device, STATE_D0);
+	if (device)
+		lpss_set_power_state(device, STATE_D0);

/* Take controller out of reset, keeping DMA in reset. */
    gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET);

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Check device validity before setting state
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/1/src/soc/intel/common/block/... 
File src/soc/intel/common/block/gspi/gspi.c:

https://review.coreboot.org/c/coreboot/+/34761/1/src/soc/intel/common/block/... 
PS1, Line 482: 	if (device)
Actually, looking at this closer, it's probably safest to put this right after setting device (line 462):
if (!device)
   return -1;
because it looks like the rest of the function is configuring the device as though it's enabled (reset, clocks, CS); i.e. it's touching a lot of registers which may not be accessible if it hasn't been assigned resources during PCI enumeration.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Check device validity before setting state
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/1/src/soc/intel/common/block/... 
File src/soc/intel/common/block/gspi/gspi.c:

https://review.coreboot.org/c/coreboot/+/34761/1/src/soc/intel/common/block/... 
PS1, Line 482: 	if (device)
> Actually, looking at this closer, it's probably safest to put this right after setting device (line  […]

Right. In fact, the control should never get here if the device we care about isn't enabled in coreboot. So, there seems to be brokenness at a different layer. Though I agree that we should have the check here and return early with an error print indicating that this condition has occurred.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Check device validity before setting state
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/1/src/soc/intel/common/block/... 
File src/soc/intel/common/block/gspi/gspi.c:

https://review.coreboot.org/c/coreboot/+/34761/1/src/soc/intel/common/block/... 
PS1, Line 455: dev->bus
Actually, looks like this is the problem. Can you see if this fixes the issue:

diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index beb12fb231..592071e8ca 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -452,15 +452,6 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev)
        struct gspi_ctrlr_params params, *p = &params;
        const struct device *device;

-       devfn = gspi_soc_bus_to_devfn(dev->bus);
-       if (devfn < 0) {
-               printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n",
-                       __func__, dev->bus);
-               return -1;
-       }
-
-       device = pcidev_path_on_root(devfn);
-
        /* Only chip select 0 is supported. */
        if (dev->cs != 0) {
                printk(BIOS_ERR, "%s: Invalid CS value: cs=%u.\n", __func__,
@@ -478,6 +469,15 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev)
                return -1;
        }

+       devfn = gspi_soc_bus_to_devfn(p->gspi_bus);
+       if (devfn < 0) {
+               printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n",
+                       __func__, gspi->bus);
+               return -1;
+       }
+
+       device = pcidev_path_on_root(devfn);
+
        /* Ensure controller is in D0 state */
        lpss_set_power_state(device, STATE_D0);

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Karthik Ramasubramanian (Code Review)]

Hello Patrick Rudolph, Justin TerAvest, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34761

to look at the new patch set (#2).

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

soc/intel/common/gspi: Use GSPI bus id to map to the controller

Currently SPI bus id is used to map to the controller in order to set
the controller state. This leads to mapping to the controller that is
not enabled. Use the GSPI id bus so that the right controller is set to
active state.

BUG=None
TEST=Boot to ChromeOS.

Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 9 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34761/2

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/1/src/soc/intel/common/block/... 
File src/soc/intel/common/block/gspi/gspi.c:

https://review.coreboot.org/c/coreboot/+/34761/1/src/soc/intel/common/block/... 
PS1, Line 455: dev->bus
> Actually, looks like this is the problem. Can you see if this fixes the issue: […]

Done

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/1/src/soc/intel/common/block/... 
File src/soc/intel/common/block/gspi/gspi.c:

https://review.coreboot.org/c/coreboot/+/34761/1/src/soc/intel/common/block/... 
PS1, Line 482: 	if (device)
> Right. […]

Done

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 2: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34761/2//COMMIT_MSG@10 
PS2, Line 10: This leads to mapping to the controller that is
            : not enabled.
It would be good to add the reason for that:
This is because the SPI bus id might not be exactly the same as GSPI bus id. In case of Intel platforms, SPI bus 0 maps to fast spi i.e. SPI going to the flash and SPI 1 .. n map to GSPI 0 to n-1.

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Karthik Ramasubramanian (Code Review)]

Hello Patrick Rudolph, Justin TerAvest, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34761

to look at the new patch set (#3).

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

soc/intel/common/gspi: Use GSPI bus id to map to the controller

Currently SPI bus id is used to map to the controller in order to set
the controller state. In certain platforms SPI bus id might not be
exactly the same as GSPI bus id. For example, in Intel platforms SPI bus
id 0 maps to fast spi i.e. SPI going to the flash and SPI bus id 1 .. n
map to GSPI bus id 0 .. n-1. Hence using SPI bus id leads to mapping to the
GSPI controller that is not enabled. Use the GSPI id bus so that the right
controller is set to active state.

BUG=None
TEST=Boot to ChromeOS.

Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 9 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34761/3

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34761/2//COMMIT_MSG@10 
PS2, Line 10: This leads to mapping to the controller that is
            : not enabled.
> It would be good to add the reason for that: […]

Done

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/3/src/soc/intel/common/block/... 
File src/soc/intel/common/block/gspi/gspi.c:

https://review.coreboot.org/c/coreboot/+/34761/3/src/soc/intel/common/block/... 
PS3, Line 473: 	if (devfn < 0) {
             : 		printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n",
             : 			__func__, dev->bus);
             : 		return -1;
             : 	}
nit: Do we need the check here now? as gspi_ctrlr_params_init would already check for valid dev and devfn?

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/3/src/soc/intel/common/block/... 
File src/soc/intel/common/block/gspi/gspi.c:

https://review.coreboot.org/c/coreboot/+/34761/3/src/soc/intel/common/block/... 
PS3, Line 473: 	if (devfn < 0) {
             : 		printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n",
             : 			__func__, dev->bus);
             : 		return -1;
             : 	}
> nit: Do we need the check here now? as gspi_ctrlr_params_init would already check for valid dev and  […]

True, gspi_calc_base_addr(), which gets called in gspi_soc_bus_to_devfn(), checks for a valid devfn and device (and programs an early BAR).

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/3/src/soc/intel/common/block/... 
File src/soc/intel/common/block/gspi/gspi.c:

https://review.coreboot.org/c/coreboot/+/34761/3/src/soc/intel/common/block/... 
PS3, Line 473: 	if (devfn < 0) {
             : 		printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n",
             : 			__func__, dev->bus);
             : 		return -1;
             : 	}
> True, gspi_calc_base_addr(), which gets called in gspi_soc_bus_to_devfn(), checks for a valid devfn  […]

Sure, will remove and add a comment explaining the reason.

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Karthik Ramasubramanian (Code Review)]

Hello Patrick Rudolph, Justin TerAvest, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34761

to look at the new patch set (#4).

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

soc/intel/common/gspi: Use GSPI bus id to map to the controller

Currently SPI bus id is used to map to the controller in order to set
the controller state. In certain platforms SPI bus id might not be
exactly the same as GSPI bus id. For example, in Intel platforms SPI bus
id 0 maps to fast spi i.e. SPI going to the flash and SPI bus id 1 .. n
map to GSPI bus id 0 .. n-1. Hence using SPI bus id leads to mapping to the
GSPI controller that is not enabled. Use the GSPI id bus so that the right
controller is set to active state.

BUG=None
TEST=Boot to ChromeOS.

Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 7 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34761/4

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/3/src/soc/intel/common/block/... 
File src/soc/intel/common/block/gspi/gspi.c:

https://review.coreboot.org/c/coreboot/+/34761/3/src/soc/intel/common/block/... 
PS3, Line 473: 	if (devfn < 0) {
             : 		printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n",
             : 			__func__, dev->bus);
             : 		return -1;
             : 	}
> Sure, will remove and add a comment explaining the reason.

Done

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 4: Code-Review+2

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 4: Code-Review+2

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[caveh jalali (Code Review)]

caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34761/4//COMMIT_MSG@17 
PS4, Line 17: None
please tag with b/135941367 and any other relevant bugs.

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[caveh jalali (Code Review)]

caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34761/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34761/4//COMMIT_MSG@16 
PS4, Line 16: 
also, this fixes a regression in CB:34449
found on AML.

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Karthik Ramasubramanian (Code Review)]

Hello Patrick Rudolph, Justin TerAvest, Subrata Banik, Aamir Bohra, Tim Wawrzynczak, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34761

to look at the new patch set (#5).

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

soc/intel/common/gspi: Use GSPI bus id to map to the controller

Currently SPI bus id is used to map to the controller in order to set
the controller state. In certain platforms SPI bus id might not be
exactly the same as GSPI bus id. For example, in Intel platforms SPI bus
id 0 maps to fast spi i.e. SPI going to the flash and SPI bus id 1 .. n
map to GSPI bus id 0 .. n-1. Hence using SPI bus id leads to mapping to the
GSPI controller that is not enabled. Use the GSPI id bus so that the right
controller is set to active state. This fixes the regression introduced
by CB:34449

BUG=b:135941367
TEST=Boot to ChromeOS.

Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 7 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34761/5

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/34761/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34761/4//COMMIT_MSG@16 
PS4, Line 16:
> also, this fixes a regression in CB:34449 […]

Done

https://review.coreboot.org/c/coreboot/+/34761/4//COMMIT_MSG@17 
PS4, Line 17: None
> please tag with b/135941367 and any other relevant bugs.

Done

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: soc/intel/common/gspi: Use GSPI bus id to map to the controller

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34761 )

Change subject: soc/intel/common/gspi: Use GSPI bus id to map to the controller
......................................................................

soc/intel/common/gspi: Use GSPI bus id to map to the controller

Currently SPI bus id is used to map to the controller in order to set
the controller state. In certain platforms SPI bus id might not be
exactly the same as GSPI bus id. For example, in Intel platforms SPI bus
id 0 maps to fast spi i.e. SPI going to the flash and SPI bus id 1 .. n
map to GSPI bus id 0 .. n-1. Hence using SPI bus id leads to mapping to the
GSPI controller that is not enabled. Use the GSPI id bus so that the right
controller is set to active state. This fixes the regression introduced
by CB:34449

BUG=b:135941367
TEST=Boot to ChromeOS.

Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34761
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Subrata Banik 
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 7 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index beb12fb..f937bd6 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -452,15 +452,6 @@
    struct gspi_ctrlr_params params, *p = &params;
    const struct device *device;

-	devfn = gspi_soc_bus_to_devfn(dev->bus);
-	if (devfn < 0) {
-		printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n",
-			__func__, dev->bus);
-		return -1;
-	}
-
-	device = pcidev_path_on_root(devfn);
-
    /* Only chip select 0 is supported. */
    if (dev->cs != 0) {
    	printk(BIOS_ERR, "%s: Invalid CS value: cs=%u.\n", __func__,
@@ -478,6 +469,13 @@
    	return -1;
    }

+	devfn = gspi_soc_bus_to_devfn(p->gspi_bus);
+	/*
+	 * devfn is already validated as part of gspi_ctrlr_params_init.
+	 * No need to revalidate it again.
+	 */
+	device = pcidev_path_on_root(devfn);
+
    /* Ensure controller is in D0 state */
    lpss_set_power_state(device, STATE_D0);