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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )
Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62566/comment/a656d4db_77ae1eb8
PS2, Line 15: Now, in this scenario, the SPI
: flash linear address range is not registered as a resource (since the
: common SPI driver in src/soc/intel/common/block/spi is shared across
: multiple SPI controllers and therefore cannot distinguish where the
: flash is actually located at)
So you are referring to UFS, right? I am not familiar with UFS, I guess it is linear mapped into the BIOS region just like SPI? If yes, the address space needs to be reserved as well, right. I just not sure what happens after boot, doe the mapping remain or is it disabled later?
Ah, yes, older platforms (APL, GLK) use eMMC, but newer platforms (ADL) use UFS. Good question, though: I don't know if the memory-mapping is disabled for eMMC/UFS later on.
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